描述 Description

The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment.The ZL30100 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable.The ZL30100 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.

特性 Features

Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input
Provides 2.048 MHz and 8.192 MHz output clocks and an 8 kHz framing pulse
Automatic entry and exit from freerun mode on reference fail
Provides DPLL lock and reference fail indication
DPLL bandwidth of 29 Hz for all rates of input references
Less than 0.6 nsecpp intrinsic jitter on all output clocks
20 MHz external master clock source: clock oscillator or crystal
Simple hardware control interface

簡介

ZL30112屬于集成電路（IC）的應用特定時鐘/定時。由制造生產的ZL30112應用特定時鐘/定時專用時鐘和計時 IC（集成電路）產品族中的產品主要用于執(zhí)行與時間或頻率信息生成和分配相關的各種操作，適合的設計環(huán)境較特定，例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設備、藍光光盤播放器、以太網設備、PCIe、SATA、光纖通道接口、車載娛樂總線等。