描述 Description

The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment.The ZL30100 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable.The ZL30100 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.

特性 Features

Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs and outputs
Supports output wander and jitter generation specifications for SONET/SDH and PDH interfaces
Accepts three input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
Provides automatic entry into Holdover and return from Holdover
Manual and automatic hitless reference switching Provides lock, holdover and accurate reference fail indication
Selectable loop filter bandwidth of 29 Hz or 922 Hz
Provides a range of clock outputs:2.048 MHz (E1), 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
19.44 MHz (SONET/SDH)* 1.544 MHz (DS1) and 3.088 MHz
a choice of 6.312 MHz (DS2), 8.448 MHz (E2), 44.736 MHz (DS3) or 34.368 MHz (E3)Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse

簡介

ZL30106屬于集成電路（IC）的應用特定時鐘/定時。由制造生產(chǎn)的ZL30106應用特定時鐘/定時專用時鐘和計時 IC（集成電路）產(chǎn)品族中的產(chǎn)品主要用于執(zhí)行與時間或頻率信息生成和分配相關(guān)的各種操作，適合的設計環(huán)境較特定，例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設備、藍光光盤播放器、以太網(wǎng)設備、PCIe、SATA、光纖通道接口、車載娛樂總線等。