描述 Description

The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment.The ZL30100 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable.The ZL30100 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.

特性 Features

Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E
Supports ITU-T G.823 and G.824 for 2048 kbps and 1544 kbps interfaces
Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
Simple hardware control interface
Accepts two input references and synchronizes to any combination of 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz inputs
Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
Provides 5 styles of 8 kHz framing pulses
Holdover frequency accuracy of 1.5 x 10-7
Lock, Holdover and selectable Out of Range indication
Selectable loop filter bandwidth of 1.8 Hz or 922 Hz
Less than 0.5 nspp jitter on all output clocks
External master clock source: clock oscillator or crystal

簡(jiǎn)介

ZL30100屬于集成電路（IC）的應(yīng)用特定時(shí)鐘/定時(shí)。由制造生產(chǎn)的ZL30100應(yīng)用特定時(shí)鐘/定時(shí)專用時(shí)鐘和計(jì)時(shí) IC（集成電路）產(chǎn)品族中的產(chǎn)品主要用于執(zhí)行與時(shí)間或頻率信息生成和分配相關(guān)的各種操作，適合的設(shè)計(jì)環(huán)境較特定，例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設(shè)備、藍(lán)光光盤(pán)播放器、以太網(wǎng)設(shè)備、PCIe、SATA、光纖通道接口、車載娛樂(lè)總線等。