描述 Description

The ZL30102 is a high-performance DPLL (digital phase-locked loop) designed for synchronization and timing control of redundant system clocks requiring Stratum 4/4E timing specifications. The ZL30102 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining a tight phase alignment between redundant primary and secondary system clocks even in the presence of high network jitter.The ZL30102 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.

特性 Features

Accepts three input references and synchronizes to any combination of 8 kHz, 1.544, 2.048, 8.192 or 16.384 MHz inputs
Synchronizes to clock-and-sync-pair to maintain minimal phase skew between redundant primary and a secondary clocks
Provides a range of clock outputs: 1.544, 2.048, 3.088, 6.312 and 16.384 MHz and either 4.096 and 8.192 MHz or 32.768 and 65.536 MHz
Provides 5 styles of 8 kHz framing pulses
Less than 0.6 nspp jitter on all output clocks
Holdover frequency accuracy of 1x10-7
Attenuates wander from 1.8 Hz
Provides Lock, Holdover and selectable Out of Range indication
Simple hardware control interface
Manual and Automatic hitless reference switching
Supports Telcordia GR-1244-CORE Stratum 4 and 4E
Supports ITU-T G.823 and G.824 for 2048 kbs and 1544 kbs interfaces
Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces

簡介

ZL30102屬于集成電路（IC）的應(yīng)用特定時(shí)鐘/定時(shí)。由制造生產(chǎn)的ZL30102應(yīng)用特定時(shí)鐘/定時(shí)專用時(shí)鐘和計(jì)時(shí) IC（集成電路）產(chǎn)品族中的產(chǎn)品主要用于執(zhí)行與時(shí)間或頻率信息生成和分配相關(guān)的各種操作，適合的設(shè)計(jì)環(huán)境較特定，例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設(shè)備、藍(lán)光光盤播放器、以太網(wǎng)設(shè)備、PCIe、SATA、光纖通道接口、車載娛樂總線等。