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ZL30105中文資料PDH/SDH System Synchronizer數(shù)據(jù)手冊(cè)Microchip規(guī)格書

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廠商型號(hào)

ZL30105

參數(shù)屬性

ZL30105 封裝/外殼為64-TQFP;包裝為卷帶(TR)剪切帶(CT)Digi-Reel? 得捷定制卷帶;類別為集成電路(IC)的應(yīng)用特定時(shí)鐘/定時(shí);產(chǎn)品描述:IC PHASE LOCK LOOP DGTL 64TQFP

功能描述

PDH/SDH System Synchronizer
IC PHASE LOCK LOOP DGTL 64TQFP

封裝外殼

64-TQFP

制造商

Microchip Microchip Technology

中文名稱

微芯科技 美國微芯科技公司

數(shù)據(jù)手冊(cè)

原廠下載下載地址下載地址二

更新時(shí)間

2025-9-9 23:01:00

人工找貨

ZL30105價(jià)格和庫存,歡迎聯(lián)系客服免費(fèi)人工找貨

ZL30105規(guī)格書詳情

描述 Description

The ZL30105 is a high-performance DPLL (digital phase-locked loop) designed for synchronization and timing control of redundant system clocks requiring Stratum 3 and SDH timing specifications. The ZL30105 generates SBI, ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between redundant primary and secondary system clocks even in the presence of high network jitter.The ZL30105 is intended to be the central timing and synchronization resource for network equipment that complies with ITU-T, Telcordia, ETSI and ANSI network specifications.

特性 Features

Accepts three input references and synchronizes to any combination of 2, 8 kHz, 1.544, 2.048, 8.192, 16.384 or 19.44 MHz inputs
Synchronizes to clock-and-sync-pair to maintain minimal phase skew between redundant system clocks
Provides a range of clock outputs: 1.544, 2.048, 3.088, 16.384, and 19.44 MHz, and either 4.096 and 8.192 MHz or 32.768 and 65.536 MHz, and a choice of 6.312, 8.448, 44.736 or 34.368 MHz
Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse
Ultra-low jitter of less than 20 psRMS on the 19.44 MHz clock
Less than 600 psp-p intrinsic jitter on all the other clock and frame pulse outputs
Holdover frequency accuracy of 1x10-8
Simple hardware control interface offers manual or automatic hitless reference switching
Supports ITU-T G.813 option 1, G.823 for 2048 kbs and G.824 for 1544 kbs interfaces
Supports Telcordia GR-1244-CORE Stratum 3/4/4E
Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces

簡(jiǎn)介

ZL30105屬于集成電路(IC)的應(yīng)用特定時(shí)鐘/定時(shí)。由制造生產(chǎn)的ZL30105應(yīng)用特定時(shí)鐘/定時(shí)專用時(shí)鐘和計(jì)時(shí) IC(集成電路)產(chǎn)品族中的產(chǎn)品主要用于執(zhí)行與時(shí)間或頻率信息生成和分配相關(guān)的各種操作,適合的設(shè)計(jì)環(huán)境較特定,例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設(shè)備、藍(lán)光光盤播放器、以太網(wǎng)設(shè)備、PCIe、SATA、光纖通道接口、車載娛樂總線等。

技術(shù)參數(shù)

更多
  • 制造商編號(hào)

    :ZL30105

  • 生產(chǎn)廠家

    :Microchip

  • Typical Jitter (12kHz-20MHz) fs RMS

    :Up to OC-3/STM-1

  • DPLLs or Paths

    :1

  • DPLL Bandwidth (Hz)

    :1.8 Hz

  • Inputs

    :3

  • Diff Outputs

    :0

  • CMOS Outputs

    :11

  • Low-Jitter Synthesizers

    :0

  • General Purpose Synthsizers

    :0

  • Diff InputFreq. Range

    :2 kHz

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