描述 Description

The?ZL30108?SONET/SDH network interface digital phase-locked loop (DPLL) provides timing and synchronization for SONET/SDH network interface cards.??Measuring just 5 mm (millimeters) x 5 mm, the ZL30108 DPLL addresses dense line card \"real estate\" constraints. The device may be used in combination with Microchip's family of analog PLLs to provide an end-to-end timing and synchronization solution for higher-speed SONET/SDH networking equipment. For example, the ZL30108 DPLL and ZL30415 analog PLL provide an easy-to-implement, compact solution for OC-12/STM-4 line cards.

特性 Features

Supports output wander and jitter generation specifications for GR-253-CORE OC-3 and G.813 STM-1 SONET/SDH interfaces
Accepts two input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
Provides a 19.44 MHz (SONET/SDH) clock output
Provides an 8 kHz framing pulse and a 2 kHz multi-frame pulse
Provides automatic entry into Holdover and return from Holdover
Hitless reference switching
Provides lock and accurate reference fail indication
Loop filter bandwidth of 29 Hz or 14 Hz
Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with GR-253-CORE OC-3 and G.813 STM-1 specifications
Ultra Compact (5 mm x 5 mm) 32-pin QFN package

簡(jiǎn)介

ZL30108屬于集成電路（IC）的應(yīng)用特定時(shí)鐘/定時(shí)。由制造生產(chǎn)的ZL30108應(yīng)用特定時(shí)鐘/定時(shí)專用時(shí)鐘和計(jì)時(shí) IC（集成電路）產(chǎn)品族中的產(chǎn)品主要用于執(zhí)行與時(shí)間或頻率信息生成和分配相關(guān)的各種操作，適合的設(shè)計(jì)環(huán)境較特定，例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設(shè)備、藍(lán)光光盤(pán)播放器、以太網(wǎng)設(shè)備、PCIe、SATA、光纖通道接口、車(chē)載娛樂(lè)總線等。