描述 Description

The ZL30110 clock rate conversion digital phase-locked loop (DPLL) provides accurate and reliable frequency conversion. The ZL30110 generates a range of clocks that are either locked to the input reference or locked to the external crystal or oscillator. In the locked mode, the reference input is continuously monitored for a failure condition. In the event of a failure, the DPLL continues to provide a stable free running clock ensuring system reliability.

特性 Features

Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz
Provides DPLL lock and reference fail indication
Automatic free run mode on reference fail
DPLL bandwidth of 922 Hz for all rates of input reference and 58 Hz for an 8 kHz input reference
Less than 5 psecrmson 25 MHz outputs, and less than 0.6 nsppintrinsic jitter on the all other outputs
Minimal input to output and output to output skew
25 MHz external master clock source: clock oscillator or crystal
Simple hardware control interface
Provides a range of output clocks:65.536 MHz TDM clock locked to the input reference
General purpose 25 MHz fan-out to 6 outputs locked to the external crystal or oscillator
General purpose 125 MHz and 66 MHz or 100 MHz locked to the external crystal or oscillator

簡介

ZL30110屬于集成電路（IC）的應(yīng)用特定時鐘/定時。由制造生產(chǎn)的ZL30110應(yīng)用特定時鐘/定時專用時鐘和計時 IC（集成電路）產(chǎn)品族中的產(chǎn)品主要用于執(zhí)行與時間或頻率信息生成和分配相關(guān)的各種操作，適合的設(shè)計環(huán)境較特定，例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設(shè)備、藍(lán)光光盤播放器、以太網(wǎng)設(shè)備、PCIe、SATA、光纖通道接口、車載娛樂總線等。