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SN65LVDS86AQDGGG4.A中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

SN65LVDS86AQDGGG4.A
廠商型號(hào)

SN65LVDS86AQDGGG4.A

功能描述

FlatLink? RECEIVER

文件大小

411.16 Kbytes

頁(yè)面數(shù)量

21 頁(yè)

生產(chǎn)廠商

TI2

中文名稱

德州儀器

網(wǎng)址

網(wǎng)址

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-8-17 10:38:00

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SN65LVDS86AQDGGG4.A價(jià)格和庫(kù)存,歡迎聯(lián)系客服免費(fèi)人工找貨

SN65LVDS86AQDGGG4.A規(guī)格書(shū)詳情

1FEATURES

2? 3:21 Data Channel Expansion at up to

178.5 Mbytes/s Throughput

? Suited for SVGA, XGA, or SXGA Display Data

Transmission From Controller to Display With

Very Low EMI

? Three Data Channels and Clock Low-Voltage

Differential Channels In and 21 Data and Clock

Low-Voltage TTL Channels Out

? Operates From a Single 3.3-V Supply

? Tolerates 4-kV Human-Body Model (HBM) ESD

? Packaged in Thin Shrink Small-Outline

Package (TSSOP) With 20-Mil Terminal Pitch

? Consumes Less Than 1 mW When Disabled

? Wide Phase-Lock Input Frequency Range

31 MHz to 68 MHz

? No External Components Required for PLL

? Inputs Meet or Exceed the Standard

Requirements of ANSI EIA/TIA-644 Standard

? Improved Replacement for the SN75LVDS86

and NSC DS90C364

? Improved Jitter Tolerance

? Qualified for Automotive Applications

DESCRIPTION

The SN65LVDS86A FlatLink? receiver contains three serial-in 7-bit parallel-out shift registers and four

low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt

of synchronous data from a compatible transmitter, such as the SN75LVDS81, '83, '84, or '85, over four

balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data at a

lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input

clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. The

SN65LVDS86A presents valid data on the falling edge of the output clock (CLKOUT).

The SN65LVDS86A requires only four line-termination resistors for the differential inputs and little or no control.

The data bus appears the same at the input to the transmitter and output of the receiver with the data

transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear

SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low

level on this signal clears all internal registers to a low level.

The SN65LVDS86A is characterized for operation over the full automotive temperature range of –40°C to 125°C.

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
TI/德州儀器
2022+
TSSOP-48
7600
原廠原裝,假一罰十
詢價(jià)
TI
25+
TSSOP
12588
原裝正品
詢價(jià)
TI(德州儀器)
23+
N/A
6000
公司只做原裝,可來(lái)電咨詢
詢價(jià)
Texas Instruments
24+
48-TSSOP
35200
一級(jí)代理/放心采購(gòu)
詢價(jià)
TIS
24+
2000
詢價(jià)
TI/德州儀器
25+
TSSOP-48
9980
只有原裝 支持實(shí)單
詢價(jià)
TI
22+
TSSOP
30000
只做原裝正品
詢價(jià)
TI
22+
TSSOP48
25000
只做原裝進(jìn)口現(xiàn)貨,專注配單
詢價(jià)
TI
TSSOP48
3000
一級(jí)代理 原裝正品假一罰十價(jià)格優(yōu)勢(shì)長(zhǎng)期供貨
詢價(jià)
TI/德州儀器
23+
QFP
11200
原廠授權(quán)一級(jí)代理、全球訂貨優(yōu)勢(shì)渠道、可提供一站式BO
詢價(jià)