SN65LVDS84AQDGGRQ1屬于集成電路（IC）的驅(qū)動器接收器收發(fā)器。由美國德州儀器公司制造生產(chǎn)的SN65LVDS84AQDGGRQ1驅(qū)動器，接收器，收發(fā)器該系列產(chǎn)品的主要功能是提供必需的硬件資源，以通過延長電纜或印制線進行通信。確切的功能會因所采用的通信協(xié)議而異，可能包括諸如瞬態(tài)抑制之類的功能，這些功能對于通信用途可能并非絕對必要，但對于可能的使用環(huán)境卻是明智之選。

1FEATURES

2· 21:3 Data Channel Compression at up to

196 Mbytes/s Throughput

· Suited for SVGA, XGA, or SXGA Data

Transmission From Controller to Display With

Very Low EMI

· 21 Data Channels Plus Clock In Low-Voltage

TTL Inputs and 3 Data Channels Plus Clock

Out Low-Voltage Differential Signaling (LVDS)

Outputs

· Operates From a Single 3.3-V Supply and

89 mW (Typ)

· Packaged in Thin Shrink Small-Outline

Package (TSSOP) With 20-Mil Terminal Pitch

· Consumes Less Than 0.54 mW When Disabled

· Wide Phase-Lock Input Frequency Range:

31 MHz to 75 MHz

· No External Components Required for PLL

· Outputs Meet or Exceed the Requirements of

ANSI EIA/TIA-644 Standard

· SSC Tracking Capability of 3% Center Spread

at 50-kHz Modulation Frequency

· Improved Replacement for SN75LVDS84 and

NSC DS90CF363A 3-V Device

· Qualified for Automotive Applications

DESCRIPTION/ORDERING INFORMATION

The SN65LVDS84AQ FlatLink? transmitter contains three 7-bit parallel-load serial-out shift registers, and four

low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of

single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a

compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A.

When transmitting, data bits D0–D20 are each loaded into registers of the SN65LVDS84AQ upon the falling

edge. The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices.

The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The

frequency of CLKOUT is the same as the input clock, CLKIN.

The SN65LVDS84AQ requires no external components and little or no control. The data bus appears the same

at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The

only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and

shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal

registers to a low level.