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SN65LVDS84AQDGG.A中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書

SN65LVDS84AQDGG.A
廠商型號(hào)

SN65LVDS84AQDGG.A

功能描述

FLATLINK TRANSMITTER

絲印標(biāo)識(shí)

65LVDS84AQ

封裝外殼

TSSOP

文件大小

518.96 Kbytes

頁面數(shù)量

22

生產(chǎn)廠商 Texas Instruments
企業(yè)簡(jiǎn)稱

TI2德州儀器

中文名稱

美國德州儀器公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-8-1 20:07:00

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SN65LVDS84AQDGG.A規(guī)格書詳情

21:3 Data Channel Compression at up to

196 Million Bytes per Second Throughput

Suited for SVGA, XGA, or SXGA Data

Transmission From Controller to Display

With Very Low EMI

21 Data Channels Plus Clock In

Low-Voltage TTL Inputs and 3 Data

Channels Plus Clock Out Low-Voltage

Differential Signaling (LVDS) Outputs

Operates From a Single 3.3-V Supply and

89 mW (Typ)

Ultralow-Power 3.3-V CMOS Version of the

SN75LVDS84. Power Consumption About

One Third of the ’LVDS84

Packaged in Thin Shrink Small-Outline

Package (TSSOP) With 20 Mil Terminal

Pitch

Consumes Less Than 0.54 mW When

Disabled

Wide Phase-Lock Input Frequency Range:

31 MHz to 75 MHz

No External Components Required for PLL

Outputs Meet or Exceed the Requirements

of ANSI EIA/TIA-644 Standard

SSC Tracking Capability of 3% Center

Spread at 50-kHz Modulation Frequency

Improved Replacement for SN75LVDS84

and NSC’s DS90CF363A 3-V Device

Available in Q-Temp Automotive

High Reliability Automotive Applications

Configuration Control / Print Support

Qualification to Automotive Standards

description

The SN75LVDS84A and SN65LVDS84AQ FlatLink transmitters contains three 7-bit parallel-load serial-out shift

registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These

functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair

conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A.

When transmitting, data bits D0 – D20 are each loaded into registers of the ’LVDS84A upon the falling edge.

The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The

three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency

of CLKOUT is the same as the input clock, CLKIN.

The ’LVDS84A requires no external components and little or no control. The data bus appears the same at the

input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only

user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut

off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers

to a low level.

The SN75LVDS84A is characterized for operation over ambient free-air temperatures of 0°C to 70°C. The

SN65LVDS84AQ is characterized for operation over the full Automotive temperature range of –40°C to 125°C.

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TI
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