SN65LVDS84AQDGGR屬于集成電路（IC）的驅(qū)動器接收器收發(fā)器。由美國德州儀器公司制造生產(chǎn)的SN65LVDS84AQDGGR驅(qū)動器，接收器，收發(fā)器該系列產(chǎn)品的主要功能是提供必需的硬件資源，以通過延長電纜或印制線進行通信。確切的功能會因所采用的通信協(xié)議而異，可能包括諸如瞬態(tài)抑制之類的功能，這些功能對于通信用途可能并非絕對必要，但對于可能的使用環(huán)境卻是明智之選。

21:3 Data Channel Compression at up to

196 Million Bytes per Second Throughput

Suited for SVGA, XGA, or SXGA Data

Transmission From Controller to Display

With Very Low EMI

21 Data Channels Plus Clock In

Low-Voltage TTL Inputs and 3 Data

Channels Plus Clock Out Low-Voltage

Differential Signaling (LVDS) Outputs

Operates From a Single 3.3-V Supply and

89 mW (Typ)

Ultralow-Power 3.3-V CMOS Version of the

SN75LVDS84. Power Consumption About

One Third of the ’LVDS84

Packaged in Thin Shrink Small-Outline

Package (TSSOP) With 20 Mil Terminal

Pitch

Consumes Less Than 0.54 mW When

Disabled

Wide Phase-Lock Input Frequency Range:

31 MHz to 75 MHz

No External Components Required for PLL

Outputs Meet or Exceed the Requirements

of ANSI EIA/TIA-644 Standard

SSC Tracking Capability of 3% Center

Spread at 50-kHz Modulation Frequency

Improved Replacement for SN75LVDS84

and NSC’s DS90CF363A 3-V Device

Available in Q-Temp Automotive

High Reliability Automotive Applications

Configuration Control / Print Support

Qualification to Automotive Standards

description

The SN75LVDS84A and SN65LVDS84AQ FlatLink transmitters contains three 7-bit parallel-load serial-out shift

registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These

functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair

conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A.

When transmitting, data bits D0 – D20 are each loaded into registers of the ’LVDS84A upon the falling edge.

The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The

three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency

of CLKOUT is the same as the input clock, CLKIN.

The ’LVDS84A requires no external components and little or no control. The data bus appears the same at the

input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only

user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut

off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers

to a low level.

The SN75LVDS84A is characterized for operation over ambient free-air temperatures of 0°C to 70°C. The

SN65LVDS84AQ is characterized for operation over the full Automotive temperature range of –40°C to 125°C.