描述 Description

The W9725G2JB is a 256M bits DDR2 SDRAM, and speed involving -25 and -3

特性 Features

?Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V
? Double Data Rate architecture: two data transfers per clock cycle
? CAS Latency: 3, 4, 5, 6 and 6
? Burst Length: 4 and 8
? Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data
? Edge-aligned with Read data and center-aligned with Write data
? DLL aligns DQ and DQS transitions with clock
? Differential clock inputs (CLK and /CLK)
? Data masks (DM) for write data
? Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS
? Posted /CAS programmable additive latency supported to make command and data bus efficiency
? Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
? Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
? Auto-precharge operation for read and write bursts
? Auto Refresh and Self Refresh modes
? Precharged Power Down and Active Power Down
? Write Data Mask
? Write Latency = Read Latency - 1 (WL = RL - 1)
? Interface: SSTL_18
? Package:TFBGA128 Ball (10.5X13.5 mm2), RoHS compliant