描述 Description

This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider to create a lower speed version of the input clock. Available divider ratios are 2, 4, 8 and 16, or straight pass-through.The differential input buffer has a unique internal termination design that allows access to the termination network through a VT?pin. This feature allows the device to easily interface to different logic standards. A VREF-AC?reference is included for AC-coupled applications.The /RESET input asynchronously resets the divider. In the pass-through function (divide by 1) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /IN).

特性 Features

? Integrated programmable clock divider and 1:2 fanout buffer
? Guaranteed AC performance over temperature and voltage:
? >2.0GHz fMAX
? <200ps tr/tf
? <15ps within device skew
? Low jitter design:
? <10psPP?total jitter
? <1psRMS?cycle-to-cycle jitter
? Unique input termination and VTPin for DC-coupled and AC-coupled Inputs; CML, PECL, LVDS and HSTL
? LVDS compatible outputs
? TTL/CMOS inputs for select and reset
? Parallel programming capability
? Programmable divider ratios of 1, 2, 4, 8 and 16
? Low voltage operation 2.5V
? Output disable function
? -40°C to 85°C temperature range
? Available in 16-pin (3mm x 3mm) MLF??package

簡介

SY89875U屬于集成電路（IC）的時鐘緩沖器驅動器。由制造生產的SY89875U時鐘緩沖器，驅動器時鐘緩沖器和驅動器集成電路產品族中的產品用于幫助信號在系統(tǒng)中傳輸，常用作頻率/時間參考信號，以同步系統(tǒng)內的活動。盡管這些器件最常用到的功能就是緩沖（即，為使信號不受驅動負載的影響而從某個信號源復制信號），但是該產品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號路徑、按某個整數值分割信號頻率，或進行所用電信號格式轉換。