描述 Description

The SY89871U is a 2.5V/3.3VLVPECL output precision clock divider capable of accepting a high-speeddifferential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clockinput signal and dividing down the frequency using a programmable divider ratioto create a frequency locked lower speed version of the input clock (BankB).Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clocksystem this would provide availability of 311MHz, 155MHz, 77MHz, or 38MHzauxiliary clock components.The differential input buffer has a unique internal termination designthat allows access to the termination network through a VT?pin. Thisfeature allows the device to easily interface to different logic standards. AVREF-AC?reference is included for AC-coupled applications.The SY89871Uincludes two phase-matched output banks. Bank A (QA) is a frequency-matchedcopy of the input. Bank B (QB0, QB1) is a divided down output of the inputfrequency. Bank A and Bank B maintain a matched delay independent of the dividersetting.

特性 Features

? Bank A: undivided pass-through (QA)
? Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1)
? Matched delay: all outputs have matched delay, independent of divider setting
? >2.5GHz fMAX
?

簡(jiǎn)介

SY89871U屬于集成電路（IC）的時(shí)鐘緩沖器驅(qū)動(dòng)器。由制造生產(chǎn)的SY89871U時(shí)鐘緩沖器，驅(qū)動(dòng)器時(shí)鐘緩沖器和驅(qū)動(dòng)器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號(hào)在系統(tǒng)中傳輸，常用作頻率/時(shí)間參考信號(hào)，以同步系統(tǒng)內(nèi)的活動(dòng)。盡管這些器件最常用到的功能就是緩沖（即，為使信號(hào)不受驅(qū)動(dòng)負(fù)載的影響而從某個(gè)信號(hào)源復(fù)制信號(hào)），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號(hào)路徑、按某個(gè)整數(shù)值分割信號(hào)頻率，或進(jìn)行所用電信號(hào)格式轉(zhuǎn)換。