描述 Description

The ADSP-2183x digital signal processors (DSPs) are members of the SHARC? family of products, featuring the next-generation SHARC-FX DSP core offering processing speeds of up to 1 GHz coupled with up to 2 MB of L2 memory for low-latency applications. For applications requiring enhanced connectivity options such as Ethernet, the ADSP-SC83x includes both a SHARC-FX DSP core and an Arm? Cortex?-M33 core. All members of the ADSP-SC83x/2183x family feature on-chip IIR and FIR accelerators, as well as an efficient auto-vectorizing compiler for C/C++ programming.

The SHARC-FX core supports scalar and vector operations on all data types in vectors up to 256 bits, including integer, fixed-point, floating-point, complex 16-bit/32-bit fixed-point, and complex 32-bit/64-bit floating-point. The processor allows eight float32 multiply/accumulate operations per cycle with no constraints on alignment. The processor comes with large register sets (32 data registers), thus reducing the need for stack save and restore. The peripherals and system architecture of the ADSP-2183x/ADSP-SC83x processors are compatible with previous SHARC processors, allowing for easy application porting.

By integrating a rich set of industry-leading system peripherals and memory, this family of processors is the platform of choice for applications that require leading-edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

APPLICATIONS

Automotive: audio for head units and amplifiers, ANC/RNC, digital cockpit, ICC, AEC/Mic beamforming, ADAS Consumer: speakers, sound bars, AVRs, conferencing systems, mixing consoles, microphone arrays

特性 Features

SHARC-FX Core Infrastructure
? 600 MHz (max) or 800 MHz (max) Core clock frequency

? 64/512 KB on-chip Level 1 (L1) Instruction/Data SRAM (with ECC) increases low latency performance

? 32/256 KB on-chip Level 1 (L1) Instruction/Data cache memory (with ECC)

? 256-bit SIMD, 4-way VLIW with large register set

? Fast on all datatypes: 32-way parallel int8 to 4-way float64

? >3x per-cycle performance increase vs SHARC+? predecessor


?Arm Core Infrastructure:?
? 400 MHz Arm Cortex-M33

? 64 KB/128 KB L1 Instruction/Data RAM with parity


?Memory?
? 1024 KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases

? Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices)


?Powerful DMA System?Innovative Digital Audio Interface (DAI) includes:?
? 8x Full SPORT interfaces w/TDM & I2S modes

? 2x S/PDIF Rx/Tx, 16 ASRC pairs

? 8x Precision Clock Generators

? 2x 4-channel PDM Mic Inputs

? 40 Buffers


?Other Peripheral Connectivity / Interfaces:?
? 2x Quad SPI, 1x Octal SPI

? MLB 3-pin

? 6x I2C,3x UARTs

? 2x Link Ports

? 16x General Purpose Timer, 1x General Purpose Counter

? 3x Watchdog Timers

? 8x ePWM outputs

? 10/100/1000 EMAC w/AVB and 1588

? 2x CAN FD

? 8-ch 12bit Housekeeping ADC

? 80 GPIO pins, 40 DAI pins

? Thermal Sensor


?Package?
? 17mm x 17mm (0.8mm pitch) 400-ball BGA_ED

? Layout-compatible with ADSP-SC592/4/6/8 and ADSP-21594


?Additional Features?
? Security and Protection
? Crypto hardware accelerators

? Fast secure boot with IP protection




? Advanced FIR and IIR accelerators running up to 800 MHz

? AEC-Q100 qualified for automotive applications