描述 Description

This octal bus transceiver is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\\ input can be used to disable the device so the buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

特性 Features

? Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
? Extended Temperature Performance of ?55°C to 125°C
? Enhanced Diminishing Manufacturing Sources (DMS) Support
? Enhanced Product-Change Notification
? Qualification Pedigree
? Typical VOLP (Output Ground Bounce) ???CC = 5 V, TA = 25°C
? Ioff and Power-Up 3-State Support Hot Insertion
? High-Drive Outputs (?24-mA IOH, 32-mA IOL)
? Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD 17
? ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
? 200-V Machine Model (A115-A)
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.