描述 Description

These octal bus transceivers are designed for asynchronous communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\\ input can be used to disable the device so the buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

特性 Features

? Typical VOLP (Output Ground Bounce) ???CC = 5 V, TA = 25°C
? Ioff and Power-Up 3-State Support Hot Insertion
? High-Drive Outputs (?32-mA IOH, 64-mA IOL)
? Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD 17
? ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
? 200-V Machine Model (A115-A)