首頁>SN65LVDS86AQDGGRQ1.A>規(guī)格書詳情
SN65LVDS86AQDGGRQ1.A中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書

廠商型號(hào) |
SN65LVDS86AQDGGRQ1.A |
功能描述 | FlatLink? RECEIVER |
文件大小 |
411.16 Kbytes |
頁面數(shù)量 |
21 頁 |
生產(chǎn)廠商 | TI2 |
中文名稱 | 德州儀器 |
網(wǎng)址 | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2025-8-22 17:24:00 |
人工找貨 | SN65LVDS86AQDGGRQ1.A價(jià)格和庫存,歡迎聯(lián)系客服免費(fèi)人工找貨 |
相關(guān)芯片規(guī)格書
更多- SN65LVDS86AQDGG
- SN65LVDS86AQ
- SN65LVDS86A
- SN65LVDS86AQDGGR
- SN65LVDS86AQDGGRQ1
- SN65LVDS86AQDGGRG4
- SN65LVDS86AQDGGG4
- SN65LVDS86ADGGRQ1
- SN65LVDS84AQ-Q1
- SN65LVDS86A-Q1
- SN65LVDS86AQDGGR
- SN65LVDS86AQDGGR.A
- SN65LVDS86AQDGGRG4
- SN65LVDS86AQDGGRG4.A
- SN65LVDS86AQDGGRQ1
- SN65LVDS86AQDGG.A
- SN65LVDS86AQDGGG4
- SN65LVDS86AQDGGG4.A
SN65LVDS86AQDGGRQ1.A規(guī)格書詳情
1FEATURES
2? 3:21 Data Channel Expansion at up to
178.5 Mbytes/s Throughput
? Suited for SVGA, XGA, or SXGA Display Data
Transmission From Controller to Display With
Very Low EMI
? Three Data Channels and Clock Low-Voltage
Differential Channels In and 21 Data and Clock
Low-Voltage TTL Channels Out
? Operates From a Single 3.3-V Supply
? Tolerates 4-kV Human-Body Model (HBM) ESD
? Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal Pitch
? Consumes Less Than 1 mW When Disabled
? Wide Phase-Lock Input Frequency Range
31 MHz to 68 MHz
? No External Components Required for PLL
? Inputs Meet or Exceed the Standard
Requirements of ANSI EIA/TIA-644 Standard
? Improved Replacement for the SN75LVDS86
and NSC DS90C364
? Improved Jitter Tolerance
? Qualified for Automotive Applications
DESCRIPTION
The SN65LVDS86A FlatLink? receiver contains three serial-in 7-bit parallel-out shift registers and four
low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt
of synchronous data from a compatible transmitter, such as the SN75LVDS81, '83, '84, or '85, over four
balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data at a
lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input
clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. The
SN65LVDS86A presents valid data on the falling edge of the output clock (CLKOUT).
The SN65LVDS86A requires only four line-termination resistors for the differential inputs and little or no control.
The data bus appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear
SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low
level on this signal clears all internal registers to a low level.
The SN65LVDS86A is characterized for operation over the full automotive temperature range of –40°C to 125°C.
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
TI |
24+ |
原廠原封 |
6523 |
進(jìn)口原裝公司百分百現(xiàn)貨可出樣品 |
詢價(jià) | ||
TI |
18+ |
TSSOP |
85600 |
保證進(jìn)口原裝可開17%增值稅發(fā)票 |
詢價(jià) | ||
TI/德州儀器 |
22+ |
TSSOP-48 |
30000 |
十七年VIP會(huì)員,誠信經(jīng)營(yíng),一手貨源,原裝正品可零售! |
詢價(jià) | ||
TI |
20+ |
NA |
53650 |
TI原裝主營(yíng)-可開原型號(hào)增稅票 |
詢價(jià) | ||
TI |
25+23+ |
TSSOP-48 |
18499 |
絕對(duì)原裝正品全新進(jìn)口深圳現(xiàn)貨 |
詢價(jià) | ||
TI(德州儀器) |
23+ |
NA |
20094 |
正納10年以上分銷經(jīng)驗(yàn)原裝進(jìn)口正品做服務(wù)做口碑有支持 |
詢價(jià) | ||
TI/德州儀器 |
22+ |
UNKNOWN |
12245 |
現(xiàn)貨,原廠原裝假一罰十! |
詢價(jià) | ||
TI |
17+ |
NA |
6200 |
100%原裝正品現(xiàn)貨 |
詢價(jià) | ||
TI |
TSSOP-48 |
1500 |
原裝長(zhǎng)期供貨! |
詢價(jià) | |||
TI |
23+ |
TSSOP |
7566 |
原廠原裝 |
詢價(jià) |