DESCRIPTION

The 18/64-Megabit Concurrent Rambus? DRAMs (RDRAM?) are extremely high-speed CMOS DRAMs organized as 2M or 8M words by 8 or 9 bits. They are capable of bursting unlimited lengths of data at 1.67 ns per byte (13.3 ns per eight bytes). The use of Rambus Signaling Level (RSL) technology permits 600 MHz transfer rates while using conventional system and board design methodologies. Low effective latency is attained by operating the two or four 2KB sense amplifiers as high speed caches, and by using random access mode (page mode) to facilitate large block transfers. Concurrent (simultaneous) bank operations permit high effective bandwidth using interleaved transactions.

FEATURES

? Compatible with Base RDRAMs

? 600 MB/s peak transfer rate per RDRAM

? Rambus Signaling Level (RSL) interface

? Synchronous, concurrent protocol for block-oriented, interleaved (overlapped) transfers

? 480 MB/s effective bandwidth for random 32 byte transfers from one RDRAM

? 13 active signals require just 32 total pins on the controller interface (including power)

? 3.3 V operation

? Additional/multiple Rambus Channels each provide an additional 600 MB/s bandwidth

? Two or four 2KByte sense amplifiers may be operated as caches for low latency access

? Random access mode enables any burst order at full bandwidth within a page

? Graphics features include write-per-bit and mask-per-bit operations

? Available in horizontal surface mount plastic package (SHP32-P-1125-0.65-K)