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CDC516

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

UseCDCVF2510AasaReplacementfor thisDevice Phase-LockLoopClockDistributionfor SynchronousDRAMApplications DistributesOneClockInputtoFourBanks ofFourOutputs SeparateOutputEnableforEachOutput Bank ExternalFeedbackPin(FBIN)IsUsedto SynchronizetheOutputstothe

CDC516

具有三態(tài)輸出的 3.3V 相位鎖定環(huán)路時鐘驅(qū)動器

The CDC516 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback output (FBOUT) to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC516 o; ? Use CDCVF2510A as a Replacement for this Device\n? Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications\n? Distributes One Clock Input to Four Banks of Four Outputs\n? Separate Output Enable for Each Output Bank\n? External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to ;

CDC516

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDC516DGG

絲?。?strong>CDC516；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

UseCDCVF2510AasaReplacementfor thisDevice Phase-LockLoopClockDistributionfor SynchronousDRAMApplications DistributesOneClockInputtoFourBanks ofFourOutputs SeparateOutputEnableforEachOutput Bank ExternalFeedbackPin(FBIN)IsUsedto SynchronizetheOutputstothe

CDC516DGG.B

絲?。?strong>CDC516；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

UseCDCVF2510AasaReplacementfor thisDevice Phase-LockLoopClockDistributionfor SynchronousDRAMApplications DistributesOneClockInputtoFourBanks ofFourOutputs SeparateOutputEnableforEachOutput Bank ExternalFeedbackPin(FBIN)IsUsedto SynchronizetheOutputstothe

CDC516DGGG4

絲?。?strong>CDC516；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

UseCDCVF2510AasaReplacementfor thisDevice Phase-LockLoopClockDistributionfor SynchronousDRAMApplications DistributesOneClockInputtoFourBanks ofFourOutputs SeparateOutputEnableforEachOutput Bank ExternalFeedbackPin(FBIN)IsUsedto SynchronizetheOutputstothe

CDC516DGGR

絲?。?strong>CDC516；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

UseCDCVF2510AasaReplacementfor thisDevice Phase-LockLoopClockDistributionfor SynchronousDRAMApplications DistributesOneClockInputtoFourBanks ofFourOutputs SeparateOutputEnableforEachOutput Bank ExternalFeedbackPin(FBIN)IsUsedto SynchronizetheOutputstothe

CDC516DGGR.B

絲印：CDC516；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

UseCDCVF2510AasaReplacementfor thisDevice Phase-LockLoopClockDistributionfor SynchronousDRAMApplications DistributesOneClockInputtoFourBanks ofFourOutputs SeparateOutputEnableforEachOutput Bank ExternalFeedbackPin(FBIN)IsUsedto SynchronizetheOutputstothe

CDC516DGG

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDC516DGGG4

3.3-V PHASE-LOCK LOOP CLOCK DRIVER