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V62SLASH24630-01XE中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

廠商型號 |
V62SLASH24630-01XE |
功能描述 | LMX1860-SEP Low-Noise, High-Frequency JESD204B/C Buffer, Multiplier and Divider |
絲印標(biāo)識 | |
封裝外殼 | HTQFP |
文件大小 |
2.98315 Mbytes |
頁面數(shù)量 |
64 頁 |
生產(chǎn)廠商 | TI1 |
中文名稱 | 德州儀器 |
網(wǎng)址 | |
數(shù)據(jù)手冊 | |
更新時間 | 2025-8-11 17:59:00 |
人工找貨 | V62SLASH24630-01XE價格和庫存,歡迎聯(lián)系客服免費(fèi)人工找貨 |
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V62SLASH24630-01XE規(guī)格書詳情
1 Features
? VID #V62/24630
– Total ionizing dose 30krad (ELDRS-free)
– Single event latch-up (SEL) immune up to
43MeV - cm2 /mg
– Single event functional interrupt (SEFI) immune
up to 43MeV - cm2 /mg
? Clock buffer for 300MHz to 15GHz frequency
? Ultra-Low Noise
– Noise floor of –159dBc/Hz at 6GHz output
– 36-fs additive jitter (100Hz to fCLK) at 6GHz
output
– 5fs additive jitter (100Hz - 100MHz)
? 4 high-frequency clocks with corresponding
SYSREF outputs
– Shared divide by 1 (Buffer), 2, 3, 4, 5, 6, 7, and
8
– Shared programmable multiplier x2, x3, and x4
? Support pin mode options to configure the device
without SPI
? LOGICLK output with corresponding SYSREF
output
– On separate divide bank
– 1, 2, 4 pre-divider
– 1 (bypass), 2, …, 1023 post divider
? 8 programmable output power levels
? Synchronized SYSREF clock outputs
– 508 delay step adjustments of less than 2.5ps
each at 12.8GHz
– Generator and repeater modes
– Windowing feature for SYSREFREQ pins to
optimize timing
? SYNC feature to all divides and multiple devices
? 2.5V operating voltage
? –55oC to 125oC operating temperature
? High Reliability
– Controlled Baseline
– One Assembly/Test Site
– One Fabrication Site
– Extended Product Life Cycle
– Product Traceability
2 Applications
? Radar imaging payload
? Communications payloads
? Command and data handling
? Data converter clocking
? Clock distribution/multiplication/division
3 Description
The LMX1860-SEP is an buffer, divider and multiplier
that features high frequency, ultra-low jitter, and
SYSREF outputs. This device combined with an ultralow
noise reference clock source is an exemplary
design for clocking data converters, especially when
sampling above 3GHz. Each of the 4 high frequency
clock outputs and additional LOGICLK output is
paired with a SYSREF output clock signal. The
SYSREF signal for JESD interfaces can either be
internally generated or passed in as an input and
re-clocked to the device clocks. This device can
distribute the multichannel, low skew, ultra-low noise
local oscillator signals to multiple mixers by disabling
the SYSREF outputs.
供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
22+ |
SOT-223 |
25000 |
只有原裝原裝,支持BOM配單 |
詢價 | |||
ST |
2511 |
TO-223 |
16900 |
電子元器件采購降本 30%!盈慧通原廠直采,砍掉中間差價 |
詢價 | ||
VANGO |
23+ |
QFN68 |
6000 |
專業(yè)配單保證原裝正品假一罰十 |
詢價 | ||
23+ |
QFN |
84 |
原裝現(xiàn)貨假一賠十 |
詢價 | |||
N/A |
2450+ |
QFN |
6540 |
只做原裝正品假一賠十為客戶做到零風(fēng)險(xiǎn)!! |
詢價 | ||
ST |
25+ |
TO-223 |
16900 |
原裝,請咨詢 |
詢價 | ||
VANGO |
17+ |
QFN68 |
880000 |
明嘉萊只做原裝正品現(xiàn)貨 |
詢價 | ||
2023+ |
13000 |
進(jìn)口原裝現(xiàn)貨 |
詢價 | ||||
UEM |
2223+ |
SOT-223 |
26800 |
只做原裝正品假一賠十為客戶做到零風(fēng)險(xiǎn) |
詢價 | ||
24+ |
SOT5 |
3629 |
原裝優(yōu)勢!房間現(xiàn)貨!歡迎來電! |
詢價 |