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首頁>V62SLASH24630-01XE>規(guī)格書詳情

V62SLASH24630-01XE中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

V62SLASH24630-01XE
廠商型號

V62SLASH24630-01XE

功能描述

LMX1860-SEP Low-Noise, High-Frequency JESD204B/C Buffer, Multiplier and Divider

絲印標(biāo)識

LMX1860

封裝外殼

HTQFP

文件大小

2.98315 Mbytes

頁面數(shù)量

64

生產(chǎn)廠商

TI1

中文名稱

德州儀器

網(wǎng)址

網(wǎng)址

數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-8-11 17:59:00

人工找貨

V62SLASH24630-01XE價格和庫存,歡迎聯(lián)系客服免費(fèi)人工找貨

V62SLASH24630-01XE規(guī)格書詳情

1 Features

? VID #V62/24630

– Total ionizing dose 30krad (ELDRS-free)

– Single event latch-up (SEL) immune up to

43MeV - cm2 /mg

– Single event functional interrupt (SEFI) immune

up to 43MeV - cm2 /mg

? Clock buffer for 300MHz to 15GHz frequency

? Ultra-Low Noise

– Noise floor of –159dBc/Hz at 6GHz output

– 36-fs additive jitter (100Hz to fCLK) at 6GHz

output

– 5fs additive jitter (100Hz - 100MHz)

? 4 high-frequency clocks with corresponding

SYSREF outputs

– Shared divide by 1 (Buffer), 2, 3, 4, 5, 6, 7, and

8

– Shared programmable multiplier x2, x3, and x4

? Support pin mode options to configure the device

without SPI

? LOGICLK output with corresponding SYSREF

output

– On separate divide bank

– 1, 2, 4 pre-divider

– 1 (bypass), 2, …, 1023 post divider

? 8 programmable output power levels

? Synchronized SYSREF clock outputs

– 508 delay step adjustments of less than 2.5ps

each at 12.8GHz

– Generator and repeater modes

– Windowing feature for SYSREFREQ pins to

optimize timing

? SYNC feature to all divides and multiple devices

? 2.5V operating voltage

? –55oC to 125oC operating temperature

? High Reliability

– Controlled Baseline

– One Assembly/Test Site

– One Fabrication Site

– Extended Product Life Cycle

– Product Traceability

2 Applications

? Radar imaging payload

? Communications payloads

? Command and data handling

? Data converter clocking

? Clock distribution/multiplication/division

3 Description

The LMX1860-SEP is an buffer, divider and multiplier

that features high frequency, ultra-low jitter, and

SYSREF outputs. This device combined with an ultralow

noise reference clock source is an exemplary

design for clocking data converters, especially when

sampling above 3GHz. Each of the 4 high frequency

clock outputs and additional LOGICLK output is

paired with a SYSREF output clock signal. The

SYSREF signal for JESD interfaces can either be

internally generated or passed in as an input and

re-clocked to the device clocks. This device can

distribute the multichannel, low skew, ultra-low noise

local oscillator signals to multiple mixers by disabling

the SYSREF outputs.

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