描述 Description

The μPD720130 is designed to perform a bridge between USB 2.0 and ATA/ATAPI. The μPD720130 complies with the Universal Serial Bus Specification Revision 2.0 full-/high-speed signaling and works up to 480 Mbps. The μPD720130 is integrated CISC processor, ATA/ATAPI controller, endpoint controller (EPC), serial interface engine (SIE), and USB2.0 transceiver into a single chip. The USB2.0 protocol and class specific protocol (bulk only protocol) are handled by USB2.0 transceiver, SIE, and EPC. And the transport layer is performed by V30MZ CISC processor which is in the μPD720130. The software to control the μPD720130 is located in an embedded ROM. In the future, the μPD720130 will be released to support external Flash Memory / EEPROM? option to update function by firmware.FEATURES
? Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 12/480 Mbps)
? Compliant with ATA/ATAPI-6 (LBA48, PIO Mode 0-4, Multi Word DMA Mode 0-2, Ultra DMA Mode 0-4)
? USB2.0 high-speed bus powered device capability
? Certified by USB implementers forum and granted with USB 2.0 high-speed Logo (TID :40320125)
? One USB2.0 high-speed transceiver / receiver with full-speed transceiver / receiver
? USB2.0 High-speed or Full-speed packet protocol sequencer (Serial Interface Engine)
? Automatic chirp assertion and full-/high-speed mode change
? USB Reset, Suspend and Resume signaling detection
? Supports power control functionality for IDE device as CD-ROM and HDD
? Supports set feature (TEST_MODE) functionality
? System Clock is generated by 30 MHz X’tal
? 2.5 V and 3.3 V power supply

特性 Features

? Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 12/480 Mbps)
? Compliant with ATA/ATAPI-6 (LBA48, PIO Mode 0-4, Multi Word DMA Mode 0-2, Ultra DMA Mode 0-4)
? USB2.0 high-speed bus powered device capability
? Certified by USB implementers forum and granted with USB 2.0 high-speed Logo (TID :40320125)
? One USB2.0 high-speed transceiver / receiver with full-speed transceiver / receiver
? USB2.0 High-speed or Full-speed packet protocol sequencer (Serial Interface Engine)
? Automatic chirp assertion and full-/high-speed mode change
? USB Reset, Suspend and Resume signaling detection
? Supports power control functionality for IDE device as CD-ROM and HDD
? Supports set feature (TEST_MODE) functionality
? System Clock is generated by 30 MHz X’tal
? 2.5 V and 3.3 V power supply