描述 Description

UCD4015 consists of two identical,independent,4-stageserial-input/parallel-output registers. Each register has independent CLOCK and RESET input as well as a single serial DATA input. ”Q” outputs are available from each of the four stages on both registers. All registers stages are D-type,master-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the reset line. Register expansion to 8 stages using one UCD4015 package or to more than 8 stages using additional UCD4015’s is possible.

特性 Features

? 12MHz (typ.) clock rate at 10V
? Maximum input current of 1μA at 18V
? Fully static operation
? 8 master-slave flip-flops plus input and output buffering