描述 Description

The UTC UCD4014B is a 8-stage synchronous parallel or serialinput/serial output registers having common CLOCK andPARALLEL/SERIAL CONTROL inputs, a SERIAL data input, andindividual parallel inputs to each register stage. Each register is aD-type master-slave flip-flop. Q6, Q7, and Q8 are outputs. With thepositive clock line transition in the CD4014 parallel/serial entry ismade into the register synchronously.In UCD4014 serial entry is controlled by the PARALLEL/SERIALCONTROL input. When the PARALLEL/SERIAL CONTROL input islow, data is serially shifted into the 8-stage register synchronously withthe positive transition of the clock line. When the PARALLEL/SERIALCONTROL input is high, data is jammed into the 8-stage register viathe parallel input lines and synchronous with the positive transition of the clock line.

特性 Features

? Up to 20V operation voltage
? 12MHz (typ.) clock rate at 10V
? Maximum input current of 1μA at 18V
? Fully static operation
? 8 master-slave flip-flops plus output buffering and control gating