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TPS70358M

雙路輸出低壓降 (LDO) 穩(wěn)壓器; ? Dual Output Voltages for Split-Supply Applications\n? Selectable Power Up Sequencing for DSP Applications\n? ?55°C to 125°C Operating Temperature\n? Output Current Range of 1 A on Regulator 1 and2 A on Regulator 2\n? Fast Transient Response\n? Voltage Options Are 3.3 V/2.5 V\n? Open Drain Power-On Reset With 120-ms Delay\n? Open Drain Power Good for Regulator 1\n? Ultralow 185-μA (typical) Quiescent Current\n? 2-μA Input Current During Standby\n? Low Noise: 78-μVRMS Without Bypass Capacitor\n? Quick Output Capacitor Discharge Feature\n? Two Manual Reset Inputs\n? 2% Accuracy Over Load and Temperature\n? Undervoltage Lockout (UVLO) Feature\n? 20-Pin Ceramic Flatpack Package\n? Thermal Shutdown Protection;

The TPS70358 is designed to provide a complete power management solution for TI DSP, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes this family ideal for any TI DSP applications with power sequencing requirement. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset inputs, and enable function, provide a complete system solution.\n The TPS70358 regulator offers very low dropout voltage and dual outputs with power up sequence control, which is designed primarily for DSP applications. These devices have low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 47-μF low ESR capacitors.\n The TPS70358 has a fixed 3.3-V/2.5-V voltage option. Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the designer to configure the source power.\n Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 250 μA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) shuts down both regulators, reducing the input current to 1 μA at TJ = 25°C.\n The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins respectively.\n The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time VOUT1 is turned on. If VOUT2 is pulled below 83% (i.e. overload condition) of its regulated voltage, VOUT1 will be turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1 is turned on first. The SEQ pin is connected to an internal pullup current source.\n For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled).\n The PG1 pin reports the voltage conditions at VOUT1. The PG1 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 1.\n The TPS70358 features a RESET (SVS, POR, or power on reset). RESET is an active low, open drain output and requires a pullup resistor for normal operation. When pulled up, RESET goes to a high impedance state (i.e. logic high) after a 120-ms delay when all three of the following conditions are met. First, VIN1 must be above the undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. Third, VOUT2 must be above approximately 95% of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1 or MR2. RESET can be used to drive power on reset or a low-battery indicator. If RESET is not used, it can be left floating.\n Internal bias voltages are powered by VIN1 and require 2.7 V for full functionality. Each regulator input has an undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V.\n \n

TPS70358M

DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS

TPS70358MHKH

DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS

TPS70358MHKH

Package：20-CDFF；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 線性 + 開(kāi)關(guān)穩(wěn)壓器 描述：IC REG LINEAR 3.3V/2.5V 20-CFP

TPS70358MHKH

Package：20-CDFF；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 穩(wěn)壓器 - 線性 描述：IC REG LINEAR 3.3V/2.5V 20-CFP

TPS70358PWP

DUAL-OUTPUTLOW-DROPOUTVOLTAGEREGULATORSWITHPOWERUPSEQUENCINGFORSPLITVOLTAGEDSPSYSTEMS

TPS70358PWP

DUAL-OUTPUT,LOWDROPOUTVOLTAGEREGULATORSWITHINTEGRATEDSVSFORSPLITVOLTAGESYSTEMS

TPS70358PWP

DUAL-OUTPUT,LOWDROPOUTVOLTAGEREGULATORSWITHINTEGRATEDSVSFORSPLITVOLTAGESYSTEMS

TPS70358PWPR

DUAL-OUTPUT,LOWDROPOUTVOLTAGEREGULATORSWITHINTEGRATEDSVSFORSPLITVOLTAGESYSTEMS