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UPD720100A

MOS INTEGRATED CIRCUIT

FEATURES ?CompliantwithUniversalSerialBusSpecificationRevision2.0(DataRate1.5/12/480Mbps) ?CompliantwithOpenHostControllerInterfaceSpecificationforUSBRev1.0a ?CompliantwithEnhancedHostControllerInterfaceSpecificationforUSBRev0.95 ?PCImulti-functiondeviceco

UPD720100A

USB2.0 HOST CONTROLLER; ? Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)\n? Compliant with Open Host Controller Interface Specification for USB Rev 1.0a\n? Compliant with Enhanced Host Controller Interface Specification for USB Rev 0.95\n? PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI\nhost controller core for high-speed signaling.\n? Root hub with five (max.) downstream facing ports which are shared by OHCI and EHCI host controller core\n? All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction.\n? Configurable number of downstream facing ports (2 to 5)\n? 32-bit 33 MHz host interface compliant to PCI Specification release 2.2.\n? Supports PCI Mobile Design Guide Revision 1.1.\n? Supports PCI-Bus Power Management Interface Specification release 1.1.\n? PCI Bus bus-master access\n? System clock is generated by 30 MHz X’tal or 48 MHz clock input.\n? Operational registers direct-mapped to PCI memory space\n? Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard implementation.\n? 3.3 V power supply, PCI signal pins have 5 V tolerant circuit.;

The μPD720100A complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for high-speed signaling and works up to 480 Mbps. The μPD720100A is integrated three host controller cores with PCI interface and USB2.0 transceivers into a single chip. Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing. μPD720100A User’s Manual: S15534EFEATURES\n? Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)\n? Compliant with Open Host Controller Interface Specification for USB Rev 1.0a\n? Compliant with Enhanced Host Controller Interface Specification for USB Rev 0.95\n? PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI\nhost controller core for high-speed signaling.\n? Root hub with five (max.) downstream facing ports which are shared by OHCI and EHCI host controller core\n? All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction.\n? Configurable number of downstream facing ports (2 to 5)\n? 32-bit 33 MHz host interface compliant to PCI Specification release 2.2.\n? Supports PCI Mobile Design Guide Revision 1.1.\n? Supports PCI-Bus Power Management Interface Specification release 1.1.\n? PCI Bus bus-master access\n? System clock is generated by 30 MHz X’tal or 48 MHz clock input.\n? Operational registers direct-mapped to PCI memory space\n? Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard implementation.\n? 3.3 V power supply, PCI signal pins have 5 V tolerant circuit.

UPD720100A

MOS INTEGRATED CIRCUIT

UPD720100AGM-8ED

MOS INTEGRATED CIRCUIT

FEATURES ?CompliantwithUniversalSerialBusSpecificationRevision2.0(DataRate1.5/12/480Mbps) ?CompliantwithOpenHostControllerInterfaceSpecificationforUSBRev1.0a ?CompliantwithEnhancedHostControllerInterfaceSpecificationforUSBRev0.95 ?PCImulti-functiondeviceco

UPD720100AGM-8EY

MOS INTEGRATED CIRCUIT

FEATURES ?CompliantwithUniversalSerialBusSpecificationRevision2.0(DataRate1.5/12/480Mbps) ?CompliantwithOpenHostControllerInterfaceSpecificationforUSBRev1.0a ?CompliantwithEnhancedHostControllerInterfaceSpecificationforUSBRev0.95 ?PCImulti-functiondeviceco

UPD720100AGM-8EY-A

MOS INTEGRATED CIRCUIT

FEATURES ?CompliantwithUniversalSerialBusSpecificationRevision2.0(DataRate1.5/12/480Mbps) ?CompliantwithOpenHostControllerInterfaceSpecificationforUSBRev1.0a ?CompliantwithEnhancedHostControllerInterfaceSpecificationforUSBRev0.95 ?PCImulti-functiondeviceco

UPD720100AS1-2C

MOS INTEGRATED CIRCUIT

FEATURES ?CompliantwithUniversalSerialBusSpecificationRevision2.0(DataRate1.5/12/480Mbps) ?CompliantwithOpenHostControllerInterfaceSpecificationforUSBRev1.0a ?CompliantwithEnhancedHostControllerInterfaceSpecificationforUSBRev0.95 ?PCImulti-functiondeviceco

UPD720100AS1-2C-A

MOS INTEGRATED CIRCUIT

FEATURES ?CompliantwithUniversalSerialBusSpecificationRevision2.0(DataRate1.5/12/480Mbps) ?CompliantwithOpenHostControllerInterfaceSpecificationforUSBRev1.0a ?CompliantwithEnhancedHostControllerInterfaceSpecificationforUSBRev0.95 ?PCImulti-functiondeviceco

UPD720100AGM-8ED

MOS INTEGRATED CIRCUIT

UPD720100AGM-8EY

MOS INTEGRATED CIRCUIT