SN74AUCH16374DGVR屬于集成電路（IC）的觸發(fā)器。由美國德州儀器公司制造生產(chǎn)的SN74AUCH16374DGVR觸發(fā)器觸發(fā)器是能夠存儲(chǔ)單個(gè)邏輯狀態(tài)或信息“位”的基本數(shù)字存儲(chǔ)器件。這些器件至少有兩個(gè)輸入；一個(gè)或多個(gè)用于傳遞要存儲(chǔ)的數(shù)據(jù)，另一個(gè)用于指示存儲(chǔ)該數(shù)據(jù)的時(shí)間點(diǎn)。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對(duì)提供給其輸入的信號(hào)有不同的響應(yīng)，可用于實(shí)現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時(shí)鐘信號(hào)時(shí)才會(huì)改變。

1FEATURES

2? Member of the Texas Instruments Widebus?

Family

? Optimized for 1.8-V Operation and Is 3.6-V I/O

Tolerant to Support Mixed-Mode Signal

Operation

? Ioff Supports Partial-Power-Down Mode

Operation

? Sub-1-V Operable

? Max tpd of 2.8 ns at 1.8 V

? Low Power Consumption, 20 μA Max ICC

? ±8-mA Output Drive at 1.8 V

? Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

? Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

? ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This 16-bit edge-triggered D-type flip-flop is

operational at 0.8-V to 2.7-V VCC, but is designed

specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUCH16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus

drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive

transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D)

inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.