SN74AUCH16244DGVR屬于集成電路（IC）的緩沖器驅動器接收器收發(fā)器。由美國德州儀器公司制造生產的SN74AUCH16244DGVR緩沖器，驅動器，接收器，收發(fā)器邏輯緩沖器、驅動器、接收器和收發(fā)器允許隔離對某個電路的邏輯信號的訪問，以用于另一電路。緩沖器將其輸入信號（不變或反相）傳遞到其輸出，并可能用于清除弱信號或驅動負載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數據總線之間進行隔離通信。

Member of the Texas Instruments

Widebus? Family

Optimized for 1.8-V Operation and is 3.6-V

I/O Tolerant to Support Mixed-Mode Signal

Operation

Ioff Supports Partial-Power-Down Mode

Operation

Sub 1-V Operable

Max tpd of 1.8 ns at 1.8 V

Low Power Consumption, 20-μA Max ICC

±8-mA Output Drive at 1.8 V

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

description/ordering information

This 16-bit buffer/driver is operational at 0.8-V to

2.7-V VCC, but is designed specifically for 1.65-V

to 1.95-V VCC operation.

The SN74AUCH16244 is designed specifically to

improve the performance and density of 3-state

memory address drivers, clock drivers, and

bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and

symmetrical active-low output-enable (OE) inputs.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.