SN74ALVCH16903屬于集成電路（IC）的通用總線功能。由美國(guó)德州儀器公司制造生產(chǎn)的SN74ALVCH16903通用總線功能通用總線功能系列產(chǎn)品是元件級(jí)產(chǎn)品，用于處理或操作一系列（通常為 8 個(gè)或更多）并行邏輯信號(hào)（稱為總線）。所執(zhí)行的功能包括臨時(shí)存儲(chǔ)要發(fā)送或接收的數(shù)據(jù)，執(zhí)行緩沖以允許輸出電流容量有限的器件（例如微處理器）通過(guò)遠(yuǎn)距離互連高速傳輸數(shù)據(jù)，以及調(diào)換或移動(dòng)總線內(nèi)的位順序等。

FEATURES

· Member of the Texas Instruments Widebus?

Family

· EPIC? (Enhanced-Performance Implanted

CMOS) Submicron Process

· Checks Parity

· Able to Cascade With a Second

SN74ALVCH16903

· ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Package Options Include Plastic 300-mil

Shrink Small-Outline (DL), Thin Shrink

Small-Outline (DGG), and Thin Very

Small-Outline (DGV) Packages

DESCRIPTION

This 12-bit universal bus driver is designed for 2.3-V

to 3.6-V VCC operation.

The SN74ALVCH16903 has dual outputs and can

operate as a buffer or an edge-triggered register. In

both modes, parity is checked on APAR, which

arrives one cycle after the data to which it applies.

The YERR output, which is produced one cycle after

APAR, is open drain.

MODE selects one of the two data paths. When

MODE is low, the device operates as an

edge-triggered register. On the positive transition of

the clock (CLK) input and when the clock-enable

(CLKEN) input is low, data set up at the A inputs is stored in the internal registers. On the positive transition of

CLK and when CLKEN is high, only data set up at the 9A–12A inputs is stored in their internal registers. When

MODE is high, the device operates as a buffer and data at the A inputs passes directly to the outputs.

11A/YERREN serves a dual purpose; it acts as a normal data bit and also enables YERR data to be clocked into

the YERR output register.

When used as a single device, parity output enable (PAROE) must be tied high; when parity input/output

(PARI/O) is low, even parity is selected and when PARI/O is high, odd parity is selected. When used in pairs and

PAROE is low, the parity sum is output on PARI/O for cascading to the second SN74ALVCH16903. When used

in pairs and PAROE is high, PARI/O accepts a partial parity sum from the first SN74ALVCH16903.

A buffered output-enable (OE) input can be used to place the 24 outputs and YERR in either a normal logic state

(high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor

drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus

lines without need for interface or pullup components.

OE does not affect the internal operation of the device. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.