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SN74ALVCH16901DGGR集成電路(IC)的通用總線功能規(guī)格書PDF中文資料

廠商型號 |
SN74ALVCH16901DGGR |
參數(shù)屬性 | SN74ALVCH16901DGGR 封裝/外殼為64-TFSOP(0.240",6.10mm 寬);包裝為管件;類別為集成電路(IC)的通用總線功能;產(chǎn)品描述:IC UNIV BUS TXRX 18BIT 64TSSOP |
功能描述 | 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS |
封裝外殼 | 64-TFSOP(0.240",6.10mm 寬) |
文件大小 |
573.71 Kbytes |
頁面數(shù)量 |
14 頁 |
生產(chǎn)廠商 | TI2 |
中文名稱 | 德州儀器 |
網(wǎng)址 | |
數(shù)據(jù)手冊 | |
更新時間 | 2025-8-7 20:00:00 |
人工找貨 | SN74ALVCH16901DGGR價格和庫存,歡迎聯(lián)系客服免費人工找貨 |
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SN74ALVCH16901DGGR規(guī)格書詳情
SN74ALVCH16901DGGR屬于集成電路(IC)的通用總線功能。由美國德州儀器公司制造生產(chǎn)的SN74ALVCH16901DGGR通用總線功能通用總線功能系列產(chǎn)品是元件級產(chǎn)品,用于處理或操作一系列(通常為 8 個或更多)并行邏輯信號(稱為總線)。所執(zhí)行的功能包括臨時存儲要發(fā)送或接收的數(shù)據(jù),執(zhí)行緩沖以允許輸出電流容量有限的器件(例如微處理器)通過遠距離互連高速傳輸數(shù)據(jù),以及調(diào)換或移動總線內(nèi)的位順序等。
Member of the Texas Instruments
Widebus? Family
UBT ? Transceiver Combines D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched, or
Clocked Mode
Operates From 1.65 V to 3.6 V
Max tpd of 4.4 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Simultaneously Generates and Checks
Parity
Option to Select Generate Parity and Check
or Feed-Through Data/Parity in A-to-B or
B-to-A Directions
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
? 2000-V Human-Body Model (A114-A)
? 200-V Machine Model (A115-A)
description/ordering information
This 18-bit (dual-octal) noninverting registered
transceiver is designed for 1.65-V to 3.6-V VCC
operation.
The SN74ALVCH16901 is a dual 9-bit to dual 9-bit
parity transceiver with registers. The device can
operate as a feed-through transceiver or it can
generate/check parity from the two 8-bit data
buses in either direction.
The SN74ALVCH16901 features independent
clock (CLKAB or CLKBA), latch-enable (LEAB or
LEBA), and dual 9-bit clock-enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and
parity-select (ODD/EVEN) inputs and separate error-signal (ERRA or ERRB) outputs for checking parity. The
direction of data flow is controlled by OEAB and OEBA. When SEL is low, the parity functions are enabled. When
SEL is high, the parity functions are disabled, and the device acts as an 18-bit registered transceiver.
產(chǎn)品屬性
更多- 產(chǎn)品編號:
SN74ALVCH16901DGGR
- 制造商:
Texas Instruments
- 類別:
集成電路(IC) > 通用總線功能
- 系列:
74ALVCH
- 包裝:
管件
- 邏輯類型:
通用總線收發(fā)器
- 電路數(shù):
18 位
- 電流 - 輸出高、低:
24mA,24mA
- 電壓 - 供電:
1.65V ~ 3.6V
- 工作溫度:
-40°C ~ 85°C
- 安裝類型:
表面貼裝型
- 封裝/外殼:
64-TFSOP(0.240",6.10mm 寬)
- 供應(yīng)商器件封裝:
64-TSSOP
- 描述:
IC UNIV BUS TXRX 18BIT 64TSSOP
供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
TI/德州儀器 |
22+ |
TSSOP |
100000 |
代理渠道/只做原裝/可含稅 |
詢價 | ||
TI/德州儀器 |
24+ |
NA/ |
26 |
優(yōu)勢代理渠道,原裝正品,可全系列訂貨開增值稅票 |
詢價 | ||
TI(德州儀器) |
2024+ |
TSSOP-64-6.1mm |
500000 |
誠信服務(wù),絕對原裝原盤 |
詢價 | ||
TI |
2018+ |
TSSOP |
11256 |
只做進口原裝正品!假一賠十! |
詢價 | ||
TI |
23+ |
NA |
19854 |
專業(yè)電子元器件供應(yīng)鏈正邁科技特價代理特價,原裝元器件供應(yīng),支持開發(fā)樣品 |
詢價 | ||
SN74ALVCH16901DGGR |
1994 |
1994 |
詢價 | ||||
TI |
23+ |
NA |
20000 |
詢價 | |||
TI/德州儀器 |
2223+ |
TSSOP |
26800 |
只做原裝正品假一賠十為客戶做到零風(fēng)險 |
詢價 | ||
TI |
24+ |
TSSOP |
25000 |
一級專營品牌全新原裝熱賣 |
詢價 | ||
MAXIM/美信 |
21+ |
TSSOP |
2856 |
百域芯優(yōu)勢 實單必成 可開13點增值稅 |
詢價 |