SN74ALVC162836DLR屬于集成電路（IC）的通用總線功能。由美國(guó)德州儀器公司制造生產(chǎn)的SN74ALVC162836DLR通用總線功能通用總線功能系列產(chǎn)品是元件級(jí)產(chǎn)品，用于處理或操作一系列（通常為 8 個(gè)或更多）并行邏輯信號(hào)（稱為總線）。所執(zhí)行的功能包括臨時(shí)存儲(chǔ)要發(fā)送或接收的數(shù)據(jù)，執(zhí)行緩沖以允許輸出電流容量有限的器件（例如微處理器）通過遠(yuǎn)距離互連高速傳輸數(shù)據(jù)，以及調(diào)換或移動(dòng)總線內(nèi)的位順序等。

FEATURES

· Member of the Texas Instruments Widebus?

Family

· Operates From 1.65 V to 3.6 V

· Max tpd of 4 ns at 3.3 V

· ±12-mA Output Drive at 3.3 V

· Output Port Has Equivalent 26-W Series

Resistors, So No External Resistors Are

Required

· Designed to Comply With JEDEC 168-Pin and

200-Pin SDRAM Buffered DIMM Specification

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This 20-bit universal bus driver is designed for 1.65-V

to 3.6-V VCC operation.

Data flow from A to Y is controlled by the

output-enable (OE) input. The device operates in the

transparent mode when the latch-enable (LE) input is

low. When LE is high, the A data is latched if the

clock (CLK) input is held at a high or low logic level. If

LE is high, the A data is stored in the latch/flip-flop on

the low-to-high transition of CLK. When OE is high,

the outputs are in the high-impedance state.

The output port includes equivalent 26-W series

resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up

or power down, OE should be tied to VCC through a

pullup resistor; the minimum value of the resistor is

determined by the current-sinking capability of the

driver.