首頁>SN65LVDS96>規(guī)格書詳情
SN65LVDS96數(shù)據(jù)手冊集成電路(IC)的驅(qū)動(dòng)器接收器收發(fā)器規(guī)格書PDF

廠商型號 |
SN65LVDS96 |
參數(shù)屬性 | SN65LVDS96 封裝/外殼為8-SOIC(0.154",3.90mm 寬);包裝為卷帶(TR)剪切帶(CT)Digi-Reel? 得捷定制卷帶;類別為集成電路(IC)的驅(qū)動(dòng)器接收器收發(fā)器;產(chǎn)品描述:IC RECEIVER 0/2 8SOIC |
功能描述 | Serdes(串行器/解串器)接收器 |
封裝外殼 | 8-SOIC(0.154",3.90mm 寬) |
制造商 | TI Texas Instruments |
中文名稱 | 德州儀器 美國德州儀器公司 |
數(shù)據(jù)手冊 | |
更新時(shí)間 | 2025-8-19 22:58:00 |
人工找貨 | SN65LVDS96價(jià)格和庫存,歡迎聯(lián)系客服免費(fèi)人工找貨 |
SN65LVDS96規(guī)格書詳情
描述 Description
The SN65LVDS96 LVDS serdes (serializer/deserializer) receiver contains three serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such asthe SN65LVDS95, over four balanced-pair conductors and expansion to 21 bits of single-ended LVTTL synchronous data at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times the LVDS input clock (CLKIN). The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN65LVDS96 presents valid data on the rising edge of the output clock (CLKOUT).
The SN65LVDS96 requires only four line termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level.
The SN65LVDS96 is characterized for operation over ambient air temperatures of -40°C to 85°C.
特性 Features
? 3:21 Data Channel Compression at up to1.428 Gigabits/s Throughput
? Suited for Point-to-Point Subsystem Communication With Very Low EMI
? 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out
? Operates From a Single 3.3-V Supply and 250 mW (Typ)
? 5-V Tolerant SHTDN Input
? Rising Clock Edge Triggered Outputs
? Bus Pins Tolerate 4-kV HBM ESD
? Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch
? Consumes A =-40°C to 85°C
? Replacement for the DS90CR216
技術(shù)參數(shù)
- 制造商編號
:SN65LVDS96
- 生產(chǎn)廠家
:TI
- Protocols
:Channel-Link I
- Parallel bus width(bits)
:21
- Signaling rate(Mbps)
:1428
- Input signal
:LVDS
- Output signal
:LVTTL
- Package Group
:TSSOP | 48
- Operating temperature range(C)
:-40 to 85
- Rating
:Catalog
供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
TI |
2016+ |
TSSOP48 |
7393 |
只做原裝,假一罰十,公司可開17%增值稅發(fā)票! |
詢價(jià) | ||
TI |
20+ |
MSOP |
65790 |
原裝優(yōu)勢主營型號-可開原型號增稅票 |
詢價(jià) | ||
TI |
06+ |
SOP8 |
3215 |
全新原裝進(jìn)口自己庫存優(yōu)勢 |
詢價(jià) | ||
TI |
24+ |
TSSOP48 |
90000 |
一級代理商進(jìn)口原裝現(xiàn)貨、假一罰十價(jià)格合理 |
詢價(jià) | ||
TI |
24+ |
MSOP8 |
20000 |
全新原廠原裝,進(jìn)口正品現(xiàn)貨,正規(guī)渠道可含稅??! |
詢價(jià) | ||
TI/德州儀器 |
25+ |
25000 |
原廠原包 深圳現(xiàn)貨 主打品牌 假一賠百 可開票! |
詢價(jià) | |||
TI |
24+ |
SOIC |
6000 |
進(jìn)口原裝正品假一賠十,貨期7-10天 |
詢價(jià) | ||
TI |
2018+ |
26976 |
代理原裝現(xiàn)貨/特價(jià)熱賣! |
詢價(jià) | |||
TI |
05+ |
TSSOP-48 |
492 |
原裝現(xiàn)貨海量庫存歡迎咨詢 |
詢價(jià) | ||
TI |
24+ |
TSSOP|48 |
55200 |
免費(fèi)送樣原盒原包現(xiàn)貨一手渠道聯(lián)系 |
詢價(jià) |