PKD01EY中文資料亞德諾數(shù)據(jù)手冊(cè)PDF規(guī)格書
| 廠商型號(hào) |
PKD01EY |
| 功能描述 | Monolithic Peak Detector with Reset-and-Hold Mode |
| 文件大小 |
402.93 Kbytes |
| 頁面數(shù)量 |
18 頁 |
| 生產(chǎn)廠商 | AD |
| 中文名稱 | 亞德諾 |
| 網(wǎng)址 | |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-8-13 20:00:00 |
| 人工找貨 | PKD01EY價(jià)格和庫存，歡迎聯(lián)系客服免費(fèi)人工找貨 |
PKD01EY規(guī)格書詳情
GENERAL DESCRIPTION
The PKD01 tracks an analog input signal until a maximum amplitude is reached. The maximum value is then retained as a peak voltage on a hold capacitor. Being a monolithic circuit, the PKD01 offers significant performance and package density advantages over hybrid modules and discrete designs without sacrificing system versatility. The matching characteristics attained in a monolithic circuit provide inherent advantages when charge injection and droop rate error reduction are primary goals.
FEATURES
Monolithic Design for Reliability and Low Cost
High Slew Rate: 0.5 V/μs
Low Droop Rate
TA = 25°C: 0.1 mV/ms
TA = 125°C: 10 mV/ms
Low Zero-Scale Error: 4 mV
Digitally Selected Hold and Reset Modes
Reset to Positive or Negative Voltage Levels
Logic Signals TTL and CMOS Compatible
Uncommitted Comparator On-Chip
Available in Die Form
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
ADI/亞德諾 |
22+ |
CDIP14 |
100000 |
代理渠道/只做原裝/可含稅 |
詢價(jià) | ||
ADI/亞德諾 |
25+ |
CDIP14 |
54658 |
百分百原裝現(xiàn)貨 實(shí)單必成 |
詢價(jià) | ||
ADI(亞德諾) |
24+ |
NA/ |
8735 |
原廠直銷,現(xiàn)貨供應(yīng),賬期支持! |
詢價(jià) | ||
AD |
24+ |
長期備有現(xiàn)貨 |
500000 |
行業(yè)低價(jià),代理渠道 |
詢價(jià) | ||
ADI |
05+ |
DIP-14 |
32 |
一級(jí)代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力 |
詢價(jià) | ||
AD |
2017+ |
DIP |
6528 |
只做原裝正品假一賠十! |
詢價(jià) | ||
AD |
CDIP14 |
220 |
一級(jí)代理 原裝正品假一罰十價(jià)格優(yōu)勢(shì)長期供貨 |
詢價(jià) | |||
ANALOG |
2025+ |
DIP |
3485 |
全新原裝、公司現(xiàn)貨熱賣 |
詢價(jià) | ||
AD |
08+ |
DIP |
3000 |
原裝現(xiàn)貨價(jià)格有優(yōu)勢(shì)量多可發(fā)貨 |
詢價(jià) | ||
AD |
24+ |
DIP-14 |
4650 |
詢價(jià) |
