特性 Features

◆ High Performance PCI Express Switch

– Sixteen PCI Express lanes (2.5Gbps), two switch ports

– Delivers 64 Gbps (8 GBps) of aggregate switching capacity

– Low latency cut-through switch architecture

– Support for Max Payload size up to 2048 bytes

– Supports one virtual channel and eight traffic classes

– PCI Express Base specification Revision 1.0a compliant

◆ Flexible Architecture with Numerous Configuration Options

– Supports automatic per port link width negotiation (x8, x4, x2,

or x1)

– Static lane reversal on all ports

– Automatic polarity inversion on all lanes

– Supports locked transactions, allowing use with legacy software

– Ability to load device configuration from serial EEPROM

– Ability to control device via SMBus

◆ Non-Transparent Port

– Crosslink support on NTB port

– Four mapping windows supported

? Each may be configured as a 32-bit memory or I/O window

? May be paired to form a 64-bit memory window

– Interprocessor communication

? Thirty-two inbound and outbound doorbells

? Four inbound and outbound message registers

? Two shared scratchpad registers

– Allows up to sixteen masters to communicate through the nontransparent port

– No limit on the number of supported outstanding transactions

through the non-transparent bridge

– Completely symmetric non-transparent bridge operation

allows similar/same configuration software to be run

– Supports direct connection to a transparent or non-transparent

port of another switch

◆ Highly Integrated Solution

– Requires no external components

– Incorporates on-chip internal memory for packet buffering and

queueing

– Integrates sixteen 2.5 Gbps embedded full duplex SerDes, 8B/

10B encoder/decoder (no separate transceivers needed)