256K x 36 and 512K x 18 Bit ZBT? Fast Static RAM

The ZBT RAM is an 8M–bit synchronous fast static RAM designed to provide Zero Bus Turnaround?. The ZBT RAM allows 100 use of bus cycles during back–to–back read/write and write/read cycles. The MCM63Z834 (organized as 256K words by 36 bits) and the MCM63Z916 (organized as 512K words by 18 bits) are fabricated in Motorola’s high performance silicon gate CMOS technology. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in communication applications. Synchronous design allows precise cycle control with the use of an external positive–edge–triggered clock (CK). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

? 3.3 V ±5 Core Power Supply, 2.5 V or 3.3 V I/O Supply

? MCM63Z834/916–10 = 10 ns Flow–Through Access/4 ns Pipelined Access (143 MHz)

MCM63Z834/916–11 = 11 ns Flow–Through Access/4.2 ns Pipelined Access (133 MHz)

MCM63Z834/916–15 = 15 ns Flow–Through Access/5 ns Pipelined Access (100 MHz)

? Selectable Read/Write Functionality (Flow–Through/Pipelined)

? Selectable Burst Sequencing Order (Linear/Interleaved)

? Internally Self–Timed Write Cycle

? Two–Cycle Deselect (Pipelined)

? Byte Write Control

? ADV Controlled Burst

? Simplified JTAG

? 100–Pin TQFP and 119–Bump PBGA Packages