The ZBT RAM is a 4M–bit synchronous fast static RAM designed to provide zero bus turnaround. The ZBT RAM allows 100 use of bus cycles during back–to–back read/write and write/read cycles. The MCM63Z736 is organized as 128K words of 36 bits each and the MCM63Z818 is organized as 256K words of 18 bits each, fabricated with high performance silicon gate CMOS technology. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in communication applications. Synchronous design allows precise cycle control with the use of an external clock (CK). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

? 3.3 V LVTTL and LVCMOS Compatible

? MCM63Z736/MCM63Z818–133 = 4.2 ns Access/7.5 ns Cycle (133 MHz)

MCM63Z736/MCM63Z818–100 = 5 ns Access/10 ns Cycle (100 MHz)

? Selectable Burst Sequencing Order (Linear/Interleaved)

? Internally Self–Timed Write Cycle

? Two–Cycle Deselect

? Byte Write Control

? ADV Controlled Burst

? 100–Pin TQFP Package