首頁>K4H281638C-TLB0>規(guī)格書詳情
K4H281638C-TLB0中文資料三星數(shù)據(jù)手冊PDF規(guī)格書
相關(guān)芯片規(guī)格書
更多K4H281638C-TLB0規(guī)格書詳情
特性 Features
? Double-data-rate architecture; two data transfers per clock cycle
? Bidirectional data strobe(DQS)
? Four banks operation
? Differential clock inputs(CK and CK)
? DLL aligns DQ and DQS transition with CK transition
? MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
? All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
? Data I/O transactions on both edges of data strobe
? Edge aligned data output, center aligned data input
? LDM,UDM/DM for write masking only
? Auto & Self refresh
? 15.6us refresh interval(4K/64ms refresh)
? Maximum burst refresh cycle : 8
? 66pin TSOP II package
產(chǎn)品屬性
- 型號：
K4H281638C-TLB0
- 制造商：
SAMSUNG
- 制造商全稱：
Samsung semiconductor
- 功能描述：
128Mb DDR SDRAM
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
SAMSUNG/三星 |
20+ |
TSOP |
35830 |
原裝優(yōu)勢主營型號-可開原型號增稅票 |
詢價 | ||
SAMSUNG/三星 |
24+ |
NA/ |
3285 |
原裝現(xiàn)貨,當(dāng)天可交貨,原型號開票 |
詢價 | ||
SAMSUNG/三星 |
22+ |
SOP |
18000 |
只做全新原裝,支持BOM配單,假一罰十 |
詢價 | ||
SAMS |
23+ |
TSOP66 |
6000 |
專業(yè)配單保證原裝正品假一罰十 |
詢價 | ||
SAM |
23+ |
NA |
288 |
專做原裝正品,假一罰百! |
詢價 | ||
SAMS |
22+ |
TSOP66 |
12245 |
現(xiàn)貨,原廠原裝假一罰十! |
詢價 | ||
SAMSUNG? |
24+ |
SOP? |
5000 |
只做原裝正品現(xiàn)貨 歡迎來電查詢15919825718 |
詢價 | ||
SAMSUNG |
22+ |
TSOP66 |
8000 |
原裝正品支持實單 |
詢價 | ||
2023+ |
SOP |
3000 |
進口原裝現(xiàn)貨 |
詢價 | |||
SAMSUNG |
TSOP-66 |
68500 |
一級代理 原裝正品假一罰十價格優(yōu)勢長期供貨 |
詢價 |
