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首頁>ISPLSI2064VL-165LT100>規(guī)格書詳情

ISPLSI2064VL-165LT100中文資料萊迪思數(shù)據(jù)手冊PDF規(guī)格書

ISPLSI2064VL-165LT100
廠商型號

ISPLSI2064VL-165LT100

功能描述

2.5V In-System Programmable SuperFAST??High Density PLD

文件大小

188.06 Kbytes

頁面數(shù)量

14

生產(chǎn)廠商

LATTICE

中文名稱

萊迪思

網(wǎng)址

網(wǎng)址

數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-8-9 10:34:00

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ISPLSI2064VL-165LT100價格和庫存,歡迎聯(lián)系客服免費人工找貨

ISPLSI2064VL-165LT100規(guī)格書詳情

描述 Description

The ispLSI 2064VL is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP).

特性 Features

? SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC

— 2000 PLD Gates

— 64 and 32 I/O Pin Versions, Four Dedicated Inputs

— 64 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100 Functional, JEDEC and Pinout Compatible with

ispLSI 2064V and 2064VE Devices

? 2.5V LOW VOLTAGE 2064 ARCHITECTURE

— Interfaces with Standard 3.3V TTL Devices (Inputs

and I/Os are 3.3V Tolerant)

— 60 mA Typical Active Current

? HIGH-PERFORMANCE E2CMOS? TECHNOLOGY

— fmax = 165MHz Maximum Operating Frequency

— tpd = 5.5ns Propagation Delay

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100 Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

? IN-SYSTEM PROGRAMMABLE

— 2.5V In-System Programmability (ISP?) Using

Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-OR

or Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-toMarket

and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

? 100 IEEE 1149.1 BOUNDARY SCAN TESTABLE

? THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

? ispDesignEXPERT? – LOGIC COMPILER AND COMPLETE

ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER?

— PC and UNIX Platforms

產(chǎn)品屬性

  • 型號:

    ISPLSI2064VL-165LT100

  • 制造商:

    Rochester Electronics LLC

  • 功能描述:

    - Bulk

供應商 型號 品牌 批號 封裝 庫存 備注 價格
LATTICE
2023+
QFP
50000
原裝現(xiàn)貨
詢價
LAT
05+
原廠原裝
4295
只做全新原裝真實現(xiàn)貨供應
詢價
LATTICE/萊迪斯
24+
QFP
22055
鄭重承諾只做原裝進口現(xiàn)貨
詢價
LATTICE
22+
QFP
2000
原裝正品現(xiàn)貨
詢價
LATTICE
25+
80LT
4860
品牌專業(yè)分銷商,可以零售
詢價
Lattice
16+
原廠封裝
10000
全新原裝正品,代理優(yōu)勢渠道供應,歡迎來電咨詢
詢價
LATTICE
24+
NA
2000
只做原裝正品現(xiàn)貨 歡迎來電查詢15919825718
詢價
Lattice
24+
QFP
66
詢價
LATTICE(萊迪思)
24+
TQFP-100(14x14)
907
深耕行業(yè)12年,可提供技術支持。
詢價
LATTICE/萊迪斯
23+
QFP
50000
全新原裝正品現(xiàn)貨,支持訂貨
詢價