首頁(yè)>ISPLSI2064VL-135LT100>規(guī)格書詳情
ISPLSI2064VL-135LT100中文資料萊迪思數(shù)據(jù)手冊(cè)PDF規(guī)格書

廠商型號(hào) |
ISPLSI2064VL-135LT100 |
功能描述 | 2.5V In-System Programmable SuperFAST??High Density PLD |
文件大小 |
188.06 Kbytes |
頁(yè)面數(shù)量 |
14 頁(yè) |
生產(chǎn)廠商 | LATTICE |
中文名稱 | 萊迪思 |
網(wǎng)址 | |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2025-8-8 20:00:00 |
人工找貨 | ISPLSI2064VL-135LT100價(jià)格和庫(kù)存,歡迎聯(lián)系客服免費(fèi)人工找貨 |
相關(guān)芯片規(guī)格書
更多- ISPLSI2064VE-135LB100
- ISPLSI2064VL-135LB100
- ISPLSI2064VE-135LJ44
- ISPLSI2064VE-135LT44
- ISPLSI2064VE-100LT100
- ISPLSI2064VE-100LJ44
- ISPLSI2064VE-135LT100
- ISPLSI2064VL-135LJ44
- ISPLSI2064VE-200LT100
- ISPLSI2064VE-200LB100
- ISPLSI2064VE-200LJ44
- ISPLSI2064VL-100LT100
- ISPLSI2064VL-100LB100
- ISPLSI2064VL-100LJ44
- ISPLSI2064VE-135LT44I
- ISPLSI2064VE-200LT44
- ISPLSI2064VE-100LB100
- ISPLSI2064VE
ISPLSI2064VL-135LT100規(guī)格書詳情
描述 Description
The ispLSI 2064VL is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP).
特性 Features
? SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100 Functional, JEDEC and Pinout Compatible with
ispLSI 2064V and 2064VE Devices
? 2.5V LOW VOLTAGE 2064 ARCHITECTURE
— Interfaces with Standard 3.3V TTL Devices (Inputs
and I/Os are 3.3V Tolerant)
— 60 mA Typical Active Current
? HIGH-PERFORMANCE E2CMOS? TECHNOLOGY
— fmax = 165MHz Maximum Operating Frequency
— tpd = 5.5ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100 Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
? IN-SYSTEM PROGRAMMABLE
— 2.5V In-System Programmability (ISP?) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-OR
or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-toMarket
and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
? 100 IEEE 1149.1 BOUNDARY SCAN TESTABLE
? THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
? ispDesignEXPERT? – LOGIC COMPILER AND COMPLETE
ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER?
— PC and UNIX Platforms
產(chǎn)品屬性
- 型號(hào):
ISPLSI2064VL-135LT100
- 制造商:
Rochester Electronics LLC
- 功能描述:
- Bulk
- 制造商:
Lattice Semiconductor Corporation
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
LATTICE(萊迪思) |
24+ |
TQFP-44(10x10) |
1 |
優(yōu)勢(shì)代理渠道,原裝正品,可全系列訂貨開增值稅票 |
詢價(jià) | ||
Lattice |
25+ |
QFP |
4500 |
全新原裝、誠(chéng)信經(jīng)營(yíng)、公司現(xiàn)貨銷售 |
詢價(jià) | ||
LATTICE |
23+ |
NA |
25060 |
只做進(jìn)口原裝,終端工廠免費(fèi)送樣 |
詢價(jià) | ||
LATTICE |
25+ |
80LT |
4860 |
品牌專業(yè)分銷商,可以零售 |
詢價(jià) | ||
LATTICE |
2023+ |
QFP |
50000 |
原裝現(xiàn)貨 |
詢價(jià) | ||
原廠原裝 |
24+ |
QFP |
9630 |
我們只做原裝正品現(xiàn)貨!量大價(jià)優(yōu)! |
詢價(jià) | ||
LATTICE |
24+ |
NA |
2000 |
只做原裝正品現(xiàn)貨 歡迎來(lái)電查詢15919825718 |
詢價(jià) | ||
23+ |
原廠封裝 |
9888 |
專做原裝正品,假一罰百! |
詢價(jià) | |||
LATTICE/萊迪斯 |
23+ |
QFP |
3000 |
一級(jí)代理原廠VIP渠道,專注軍工、汽車、醫(yī)療、工業(yè)、 |
詢價(jià) | ||
LATTICE |
24+ |
QFP128 |
6980 |
原裝現(xiàn)貨,可開13%稅票 |
詢價(jià) |