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HD74HC4017FPEL中文資料瑞薩數(shù)據(jù)手冊PDF規(guī)格書
HD74HC4017FPEL規(guī)格書詳情
描述 Description
The HD74HC4017 is a 5-stage divide-by-10 Johnson counter with ten decoded outputs and a carry-out bit. High-speed operation and spike-free outputs are obtained by use of the Johnson decade counter configuration.
The ten decoded outputs are normally low and go high only at their respective decimal time periods. A high signal on Reset R asynchronously clears the decade counter and sets the carry output and Y0 high. With CE low, the count is advanced on a low-to-high transition at C input. Alternatively, if C is high, the count is advanced on a high-to-low transition at CE. Each decoded output remains high for one full clock cycle. The carry output is high while Q0, Q1, Q2, Q3 or Q4 is high, then is low while Q5, Q6, Q7, Q8 or Q9 is high.
特性 Features
? High Speed Operation
? High Output Current: Fanout of 10 LSTTL Loads
? Wide Operating Voltage: VCC = 2 to 6 V
? Low Input Current: 1 μA max
? Low Quiescent Supply Current: ICC (static) = 4 μA max (Ta = 25°C)
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---|---|---|---|---|---|---|---|
RENESAS/瑞薩 |
24+ |
NA/ |
3358 |
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詢價 | ||
HITACHI |
23+ |
SOP |
20000 |
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詢價 | ||
HITACHI |
99+ |
SOP16 |
1000 |
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HIT |
23+ |
SOP |
7000 |
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詢價 | ||
HITACHI |
23+ |
NA |
2279 |
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詢價 | ||
HITACHI |
24+ |
SOP16 |
2000 |
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詢價 | ||
HITACHI |
05+ |
原廠原裝 |
6341 |
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詢價 | ||
HITACHI |
22+ |
DIP16 |
45000 |
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詢價 | ||
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25+23+ |
DIP16 |
33882 |
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詢價 | ||
RENESAS |
2450+ |
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18500 |
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詢價 |