描述 Description

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input Gis low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse.When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuitsare designed to prevent false clocking by transitions at the G input.

特性 Features

? High Speed Operation: tpd= 13 ns typ (CL= 50 pF)

? High Output Current: Fanout of 10 LSTTL Loads

? Wide Operating Voltage: VCC= 2 to 6 V

? Low Input Current: 1 μA max

? Low Quiescent Supply Current: ICC(static) = 4 μA max (Ta = 25°C)