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首頁>HD74HC373FPEL>規(guī)格書詳情

HD74HC373FPEL中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書

HD74HC373FPEL
廠商型號(hào)

HD74HC373FPEL

功能描述

Octal D-type Transparent Latches (with 3-state outputs)/Octal D-type Transparent Latches (with inverted 3-state outputs)

文件大小

119.33 Kbytes

頁面數(shù)量

10

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡(jiǎn)稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
RENESAS
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-8-2 18:03:00

人工找貨

HD74HC373FPEL價(jià)格和庫存,歡迎聯(lián)系客服免費(fèi)人工找貨

HD74HC373FPEL規(guī)格書詳情

描述 Description

When the latch enable input is high, the Q outputs of HD74HC373 will follow the D inputs and the Q outputs of HD74HC533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.

特性 Features

? High Speed Operation: tpd (D to Q) = 16 ns typ (CL = 50 pF)

? High Output Current: Fanout of 15 LSTTL Loads

? Wide Operating Voltage: VCC = 2 to 6 V

? Low Input Current: 1 μA max

? Low Quiescent Supply Current: ICC (static) = 4 μA max (Ta = 25°C)

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220
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HD
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