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CD74HC112M96

Marking：HC112M；Package：SOIC；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1Features ?Hysteresisonclockinputsforimprovednoise immunityandincreasedinputriseandfalltimes ?Asynchronoussetandreset ?Complementaryoutputs ?Bufferedinputs ?TypicalfMAX=60MHzatVCC=5V,CL=15pF,TA =25℃ ?Fanout(overtemperaturerange) –Standardoutput

TI1Texas Instruments

德州儀器美國(guó)德州儀器公司

CD74HC112MT

Marking：HC112M；Package：SOIC；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1Features ?Hysteresisonclockinputsforimprovednoise immunityandincreasedinputriseandfalltimes ?Asynchronoussetandreset ?Complementaryoutputs ?Bufferedinputs ?TypicalfMAX=60MHzatVCC=5V,CL=15pF,TA =25℃ ?Fanout(overtemperaturerange) –Standardoutput

TI1Texas Instruments

德州儀器美國(guó)德州儀器公司

CD74HC112NS

Marking：HC112M；Package：SO；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1Features ?Hysteresisonclockinputsforimprovednoise immunityandincreasedinputriseandfalltimes ?Asynchronoussetandreset ?Complementaryoutputs ?Bufferedinputs ?TypicalfMAX=60MHzatVCC=5V,CL=15pF,TA =25℃ ?Fanout(overtemperaturerange) –Standardoutput

TI1Texas Instruments

德州儀器美國(guó)德州儀器公司

CD74HC112NSR

Marking：HC112M；Package：SO；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1Features ?Hysteresisonclockinputsforimprovednoise immunityandincreasedinputriseandfalltimes ?Asynchronoussetandreset ?Complementaryoutputs ?Bufferedinputs ?TypicalfMAX=60MHzatVCC=5V,CL=15pF,TA =25℃ ?Fanout(overtemperaturerange) –Standardoutput

TI1Texas Instruments

德州儀器美國(guó)德州儀器公司

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