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CD74HC03M96.A

Marking：HC03M；Package：SOIC；High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain

Features ?BufferedInputs ?TypicalPropagationDelay:8nsatVCC=5V, CL=15pF,TA=25oC ?OutputPull-upto10V ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?WideOpera

CD74HC03MT

Marking：HC03M；Package：SOIC；High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain

Features ?BufferedInputs ?TypicalPropagationDelay:8nsatVCC=5V, CL=15pF,TA=25oC ?OutputPull-upto10V ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?WideOpera

CD74HC109M

Marking：HC109M；Package：SOIC；Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features ?AsynchronousSetandReset ?SchmittTriggerClockInputs ?TypicalfMAX=54MHzatVCC=5V,CL=15pF, TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?Wi

CD74HC109M96

Marking：HC109M；Package：SOIC；Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features ?AsynchronousSetandReset ?SchmittTriggerClockInputs ?TypicalfMAX=54MHzatVCC=5V,CL=15pF, TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?Wi

CD74HC109M96.A

Marking：HC109M；Package：SOIC；Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features ?AsynchronousSetandReset ?SchmittTriggerClockInputs ?TypicalfMAX=54MHzatVCC=5V,CL=15pF, TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?Wi

CD74HC112M96

Marking：HC112M；Package：SOIC；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1Features ?Hysteresisonclockinputsforimprovednoise immunityandincreasedinputriseandfalltimes ?Asynchronoussetandreset ?Complementaryoutputs ?Bufferedinputs ?TypicalfMAX=60MHzatVCC=5V,CL=15pF,TA =25℃ ?Fanout(overtemperaturerange) –Standardoutput

CD74HC112MT

Marking：HC112M；Package：SOIC；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1Features ?Hysteresisonclockinputsforimprovednoise immunityandincreasedinputriseandfalltimes ?Asynchronoussetandreset ?Complementaryoutputs ?Bufferedinputs ?TypicalfMAX=60MHzatVCC=5V,CL=15pF,TA =25℃ ?Fanout(overtemperaturerange) –Standardoutput

CD74HC112NS

Marking：HC112M；Package：SO；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1Features ?Hysteresisonclockinputsforimprovednoise immunityandincreasedinputriseandfalltimes ?Asynchronoussetandreset ?Complementaryoutputs ?Bufferedinputs ?TypicalfMAX=60MHzatVCC=5V,CL=15pF,TA =25℃ ?Fanout(overtemperaturerange) –Standardoutput

CD74HC112NSR

Marking：HC112M；Package：SO；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1Features ?Hysteresisonclockinputsforimprovednoise immunityandincreasedinputriseandfalltimes ?Asynchronoussetandreset ?Complementaryoutputs ?Bufferedinputs ?TypicalfMAX=60MHzatVCC=5V,CL=15pF,TA =25℃ ?Fanout(overtemperaturerange) –Standardoutput

CD74HC123M96.A

Marking：HC123M；Package：SOIC；High-Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets

Features ?OverridingResetTerminatesOutputPulse ?TriggeringFromtheLeadingorTrailingEdge ?QandQBufferedOutputs ?SeparateResets ?WideRangeofOutput-PulseWidths ?SchmittTriggeronBothAandBInputs ?Fanout(OverTemperatureRange) -StandardOutputs........