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首頁>CDCLVP2102RGTTG4.B>規(guī)格書詳情

CDCLVP2102RGTTG4.B中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書

CDCLVP2102RGTTG4.B
廠商型號(hào)

CDCLVP2102RGTTG4.B

功能描述

CDCLVP2102 Four-LVPECL Output, High-Performance Clock Buffer

絲印標(biāo)識(shí)

2102

封裝外殼

VQFN

文件大小

810.13 Kbytes

頁面數(shù)量

28

生產(chǎn)廠商

TI2

中文名稱

德州儀器

網(wǎng)址

網(wǎng)址

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-8-24 18:30:00

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CDCLVP2102RGTTG4.B價(jià)格和庫存,歡迎聯(lián)系客服免費(fèi)人工找貨

CDCLVP2102RGTTG4.B規(guī)格書詳情

1 Features

1? Dual 1:2 Differential Buffer

? Two Clock Inputs

? Universal Inputs Can Accept LVPECL, LVDS,

LVCMOS/LVTTL

? Four LVPECL Outputs

? Maximum Clock Frequency: 2 GHz

? Maximum Core Current Consumption: 48 mA

? Very Low Additive Jitter: <100 fs, RMS in 10-kHz

to 20-MHz Offset Range

? 2.375-V to 3.6-V Device Power Supply

? Maximum Propagation Delay: 450 ps

? Maximum Within Bank Output Skew: 10 ps

? LVPECL Reference Voltage, VAC_REF, Available

for Capacitive-Coupled Inputs

? Industrial Temperature Range: –40°C to +85°C

? Supports 105°C PCB Temperature (Measured

with a Thermal Pad)

? Available in 3-mm × 3-mm, 16-Pin VQFN (RGT)

Package

? ESD Protection Exceeds 2000 V (HBM)

2 Applications

? Wireless Communications

? Telecommunications/Networking

? Medical Imaging

? Test and Measurement Equipment

3 Description

The CDCLVP2102 is a highly versatile, low additive

jitter buffer that can generate four copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS

inputs for a variety of communication applications. It

has a maximum clock frequency up to 2 GHz. Each

buffer block consists of one input that feeds two

LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to

20 MHz, and overall output skew is as low as 10 ps,

making the device a perfect choice for use in

demanding applications.

The CDCLVP2102 clock buffer distributes two clock

inputs (IN0, IN1) to four pairs of differential LVPECL

clock outputs (OUT0, OUT3) with minimum skew for clock distribution. Each buffer block consists of one

input that feeds two LVPECL clock outputs. The

inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2102 is specifically designed for driving

50-Ω transmission lines. When driving the inputs in

single-ended mode, the LVPECL bias voltage

(VAC_REF) should be applied to the unused negative

input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2102 is characterized for operation from

–40°C to +85°C and is available in a 3-mm × 3-mm, VQFN-16 package.

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫存 備注 價(jià)格
TI(德州儀器)
2024+
N/A
500000
誠信服務(wù),絕對(duì)原裝原盤
詢價(jià)
BB/TI
10+
QFN
21
一級(jí)代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力
詢價(jià)
TI/德州儀器
25+
25000
原廠原包 深圳現(xiàn)貨 主打品牌 假一賠百 可開票!
詢價(jià)
TI
22+
QFN
8000
原裝正品支持實(shí)單
詢價(jià)
TI/德州儀器
21+
VQFN28
36680
只做原裝,質(zhì)量保證
詢價(jià)
TI/德州儀器
23+
VQFN28
18204
原裝正品代理渠道價(jià)格優(yōu)勢(shì)
詢價(jià)
TI/德州儀器
22+
VQFN28
12140
原裝正品
詢價(jià)
TI
16+
BGA
2500
進(jìn)口原裝現(xiàn)貨/價(jià)格優(yōu)勢(shì)!
詢價(jià)
TI
1725+
VQFN28
7500
只做原裝進(jìn)口,假一罰十
詢價(jià)
TI
三年內(nèi)
1983
只做原裝正品
詢價(jià)