最新无码a∨在线观看,一本av高清一区二区三区,亚洲熟妇色l20p,宅男噜噜69av,中出あ人妻熟女中文字幕

首頁>CDCLVP2102RGTT.B>規(guī)格書詳情

CDCLVP2102RGTT.B中文資料德州儀器數據手冊PDF規(guī)格書

CDCLVP2102RGTT.B
廠商型號

CDCLVP2102RGTT.B

功能描述

CDCLVP2102 Four-LVPECL Output, High-Performance Clock Buffer

絲印標識

2102

封裝外殼

VQFN

文件大小

810.13 Kbytes

頁面數量

28

生產廠商

TI2

中文名稱

德州儀器

網址

網址

數據手冊

下載地址一下載地址二到原廠下載

更新時間

2025-8-22 10:44:00

人工找貨

CDCLVP2102RGTT.B價格和庫存,歡迎聯系客服免費人工找貨

CDCLVP2102RGTT.B規(guī)格書詳情

1 Features

1? Dual 1:2 Differential Buffer

? Two Clock Inputs

? Universal Inputs Can Accept LVPECL, LVDS,

LVCMOS/LVTTL

? Four LVPECL Outputs

? Maximum Clock Frequency: 2 GHz

? Maximum Core Current Consumption: 48 mA

? Very Low Additive Jitter: <100 fs, RMS in 10-kHz

to 20-MHz Offset Range

? 2.375-V to 3.6-V Device Power Supply

? Maximum Propagation Delay: 450 ps

? Maximum Within Bank Output Skew: 10 ps

? LVPECL Reference Voltage, VAC_REF, Available

for Capacitive-Coupled Inputs

? Industrial Temperature Range: –40°C to +85°C

? Supports 105°C PCB Temperature (Measured

with a Thermal Pad)

? Available in 3-mm × 3-mm, 16-Pin VQFN (RGT)

Package

? ESD Protection Exceeds 2000 V (HBM)

2 Applications

? Wireless Communications

? Telecommunications/Networking

? Medical Imaging

? Test and Measurement Equipment

3 Description

The CDCLVP2102 is a highly versatile, low additive

jitter buffer that can generate four copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS

inputs for a variety of communication applications. It

has a maximum clock frequency up to 2 GHz. Each

buffer block consists of one input that feeds two

LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to

20 MHz, and overall output skew is as low as 10 ps,

making the device a perfect choice for use in

demanding applications.

The CDCLVP2102 clock buffer distributes two clock

inputs (IN0, IN1) to four pairs of differential LVPECL

clock outputs (OUT0, OUT3) with minimum skew for clock distribution. Each buffer block consists of one

input that feeds two LVPECL clock outputs. The

inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2102 is specifically designed for driving

50-Ω transmission lines. When driving the inputs in

single-ended mode, the LVPECL bias voltage

(VAC_REF) should be applied to the unused negative

input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2102 is characterized for operation from

–40°C to +85°C and is available in a 3-mm × 3-mm, VQFN-16 package.

供應商 型號 品牌 批號 封裝 庫存 備注 價格
TI/德州儀器
24+
VQFN28
3000
訂貨中主營TI
詢價
TI/德州儀器
22+
VQFN28
12140
原裝正品
詢價
TI
16+
BGA
2500
進口原裝現貨/價格優(yōu)勢!
詢價
Texas Instruments
23+
ROHS
57
正品原裝貨價格低
詢價
TI
22+
28VQFN
9000
原廠渠道,現貨配單
詢價
TI/德州儀器
24+
NA
38522
只做全新原裝進口現貨
詢價
TI
24+
QFN28
5000
只做原裝公司現貨
詢價
TI/德州儀器
24+
QFN
3177
只供應原裝正品 歡迎詢價
詢價
TI
22+
QFN
8000
原裝正品支持實單
詢價
BB/TI
21+
QFN
21
原裝現貨假一賠十
詢價