ADSP-21261SKBCZ150屬于集成電路（IC）的DSP（數(shù)字信號處理器）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADSP-21261SKBCZ150DSP（數(shù)字信號處理器）數(shù)字信號處理器是類似于微處理器或微控制器的器件，但區(qū)別在于其內(nèi)部架構(gòu)經(jīng)修改，適用于對連續(xù)數(shù)據(jù)流連續(xù)執(zhí)行以乘法和加法運(yùn)算為主的算法，而不是以條件邏輯或大量并發(fā)進(jìn)程為主的算法。該器件通常用于諸如音頻或視頻信號處理等應(yīng)用。

GENERAL DESCRIPTION

The ADSP-21261/ADSP-21262/ADSP-21266 SHARC? DSPs are members of the SIMD SHARC family of DSPs featuring Analog Devices, Inc., Super Harvard Architecture. The ADSP-2126x is source code compatible with the ADSP-21160 and ADSP-21161 DSPs as well as with first generation ADSP- 2106x SHARC processors in SISD (single-instruction, single data) mode. Like other SHARC DSPs, the ADSP-2126x are 32-bit/40-bit floating-point processors optimized for high performance audio applications with dual-ported on-chip SRAM, mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital application interface.

SUMMARY

High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing

Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs

Processes high performance audio while enabling low system costs

Audio decoders and postprocessor algorithms support nonvolatile memory that can be configured to contain a combination of PCM 96 kHz, Dolby Digital, Dolby Digital Surround EX, DTS-ES Discrete 6.1, DTS-ES Matrix 6.1, DTS 96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMA-PRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and DTS Neo:6

Various multichannel surround sound decoders are contained in ROM. For configurations of decoder algorithms, see Table 3 on Page 4.

Single-instruction multiple-data (SIMD) computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file

High bandwidth I/O—a parallel port, an SPI port, 6 serial ports, a Digital application interface (DAI), and JTAG

DAI incorporates two precision clock generators (PCGs), an input data port (IDP) that includes a parallel data acquisition port (PDAP), and 3 programmable timers, all under software control by the signal routing unit (SRU)

On-chip memory—up to 2M bits on-chip SRAM and a dedicated 4M bits on-chip mask-programmable ROM

The ADSP-2126x processors are available with a 150 MHz or a 200 MHz core instruction rate. For complete ordering information, see Ordering Guide on Page 45.