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CD74ACT112M

Marking：ACT112M；Package：SOIC；DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays 24-mAOutputDriveCurrent Fanoutto15FDevices SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,Me

TI2Texas Instruments

德州儀器美國德州儀器公司

CD74ACT112M96

Marking：ACT112M；Package：SOIC；DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays 24-mAOutputDriveCurrent Fanoutto15FDevices SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,Me

TI2Texas Instruments

德州儀器美國德州儀器公司

CD74ACT112M96.A

Marking：ACT112M；Package：SOIC；DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays 24-mAOutputDriveCurrent Fanoutto15FDevices SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,Me

TI2Texas Instruments

德州儀器美國德州儀器公司

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