最新无码a∨在线观看,一本av高清一区二区三区,亚洲熟妇色l20p,宅男噜噜69av,中出あ人妻熟女中文字幕

首頁>74LVCH16373ADGV>規(guī)格書詳情

74LVCH16373ADGV集成電路(IC)的鎖存器規(guī)格書PDF中文資料

74LVCH16373ADGV
廠商型號(hào)

74LVCH16373ADGV

參數(shù)屬性

74LVCH16373ADGV 封裝/外殼為48-TFSOP(0.173",4.40mm 寬);包裝為卷帶(TR);類別為集成電路(IC)的鎖存器;產(chǎn)品描述:74LVCH16373ADGV-Q100/SOT480/TS

功能描述

16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

封裝外殼

48-TFSOP(0.173",4.40mm 寬)

文件大小

261.55 Kbytes

頁面數(shù)量

15

生產(chǎn)廠商

NEXPERIA Nexperia B.V. All rights reserved

中文名稱

安世 安世半導(dǎo)體(中國)有限公司

網(wǎng)址

網(wǎng)址

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-8-17 16:30:00

人工找貨

74LVCH16373ADGV價(jià)格和庫存,歡迎聯(lián)系客服免費(fèi)人工找貨

74LVCH16373ADGV規(guī)格書詳情

1. General description

The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches with 3-state outputs.

The devices can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The

devices feature two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each

controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the

latches are transparent, a latch output will change each time its corresponding D-input changes.

When nLE is LOW the latches store the information that was present at the inputs a set-up time

preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a

high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices

as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

Bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs.

2. Features and benefits

? Overvoltage tolerant inputs to 5.5 V

? Wide supply voltage range from 1.2 V to 3.6 V

? CMOS low power dissipation

? MULTIBYTE flow-through standard pinout architecture

? Multiple low inductance supply pins for minimum noise and ground bounce

? Direct interface with TTL levels

? All data inputs have bus hold (74LVCH16373A only)

? IOFF circuitry provides partial Power-down mode operation

? Complies with JEDEC standards:

? JESD8-7A (1.65 V to 1.95 V)

? JESD8-5A (2.3 V to 2.7 V)

? JESD8-C/JESD36 (2.7 V to 3.6 V)

? ESD protection:

? HBM JESD22-A114F exceeds 2000 V

? MM JESD22-A115-B exceeds 200 V

? CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V

? Specified from -40 °C to +85 °C and -40 °C to +125 °C

產(chǎn)品屬性

  • 產(chǎn)品編號(hào):

    74LVCH16373ADGV-QJ

  • 制造商:

    Nexperia USA Inc.

  • 類別:

    集成電路(IC) > 鎖存器

  • 系列:

    Automotive, AEC-Q100, 74LVCH

  • 包裝:

    卷帶(TR)

  • 邏輯類型:

    D 型透明鎖存器

  • 電路:

    8:8

  • 輸出類型:

    三態(tài)

  • 電壓 - 供電:

    1.65V ~ 3.6V

  • 延遲時(shí)間 - 傳播:

    2.9ns

  • 電流 - 輸出高、低:

    24mA,24mA

  • 工作溫度:

    -40°C ~ 125°C

  • 安裝類型:

    表面貼裝型

  • 封裝/外殼:

    48-TFSOP(0.173",4.40mm 寬)

  • 供應(yīng)商器件封裝:

    48-TSSOP

  • 描述:

    74LVCH16373ADGV-Q100/SOT480/TS

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫存 備注 價(jià)格
PHI
24+
SSOP48
662
詢價(jià)
PHI
2402+
SSOP48
8324
原裝正品!實(shí)單價(jià)優(yōu)!
詢價(jià)
TI
2025+
TVSOP-48
16000
原裝優(yōu)勢(shì)絕對(duì)有貨
詢價(jià)
TI/德州儀器
25+
TVSOP-48
860000
明嘉萊只做原裝正品現(xiàn)貨
詢價(jià)
Nexperia(安世)
24+
TSSOP48
3238
原裝現(xiàn)貨,免費(fèi)供樣,技術(shù)支持,原廠對(duì)接
詢價(jià)
TI/德州儀器
22+
TSSOP48
25000
只做原裝,原裝,假一罰十
詢價(jià)
NEXPERIA/安世
2447
SMD
100500
一級(jí)代理專營品牌!原裝正品,優(yōu)勢(shì)現(xiàn)貨,長(zhǎng)期排單到貨
詢價(jià)
Texas Instruments(德州儀器)
22+
NA
500000
萬三科技,秉承原裝,購芯無憂
詢價(jià)
Texas Instruments
2022+
48-TVSOP
38550
全新原裝 支持表配單 中國著名電子元器件獨(dú)立分銷
詢價(jià)
PHI
01+
SSOP/48
662
原裝現(xiàn)貨海量庫存歡迎咨詢
詢價(jià)