74LVC1G123DCURG4屬于集成電路（IC）的多諧振蕩器。由美國(guó)德州儀器公司制造生產(chǎn)的74LVC1G123DCURG4多諧振蕩器多諧振蕩器是簡(jiǎn)單的雙態(tài)器件，盡管它們的典型使用方式在很大程度上具有模擬特性，但通常被認(rèn)為是數(shù)字邏輯元器件。單穩(wěn)型也稱(chēng)為“單發(fā)”，具有一種穩(wěn)定狀態(tài)；但施加觸發(fā)信號(hào)可使它們離開(kāi)此狀態(tài)一段時(shí)間，該時(shí)間通常由所連接電容器的值來(lái)確定。這些器件對(duì)于去彈跳開(kāi)關(guān)觸頭等應(yīng)用非常有用。非穩(wěn)型沒(méi)有穩(wěn)定狀態(tài)，在兩個(gè)狀態(tài)之間按一定頻率持續(xù)轉(zhuǎn)換，該頻率通常也是由所連接電容器的值來(lái)確定。

1 Features

? Available in the Texas Instruments

NanoFree? Package

? Supports 5V VCC Operation

? Inputs Accept Voltages to 5.5V

? Max tpd of 8ns at 3.3V

? Supports Mixed-Mode Voltage Operation on

All Ports

? Supports Down Translation to VCC

? Schmitt-Trigger Circuitry on A and B Inputs for

Slow Input Transition Rates

? Edge Triggered From Active-High or Active-Low

Gated Logic Inputs

? Retriggerable for Very Long Output Pulses, Up to

100% Duty Cycle

? Overriding Clear Terminates Output Pulse

? Glitch-Free Power-Up Reset on Outputs

? Ioff Supports Live Insertion, Partial-Power-Down

Mode, and Back-Drive Protection

? Latch-Up Performance Exceeds 100 mA Per JESD

78, Class II

? ESD Protection Exceeds JESD 22

– 2000V Human-Body Model (A114-A)

– 200V Machine Model (A115-A)

– 1000V Charged-Device Model (C101)

2 Applications

? AV Receivers

? Blu-ray Players and Home Theaters

? DVD Recorders and Players

? Desktop PCs or Notebook PCs

? Digital Radio and Internet Radio Players

? Digital Video Cameras (DVC)

? Embedded PCs

? GPS: Personal Navigation Devices

? Mobile Internet Devices

? Network Attached Storage (NAS)

? Personal Digital Assistant (PDA)

? Server PSU

? Solid-State Drive (SSD): Client and Enterprise

? Video Analytics Servers

? Wireless Headsets, Keyboards, and Mice

3 Description

The SN74LVC1G123 device is a single retriggerable

monostable multivibrator designed for 1.65V to 5.5V

VCC operation.

This monostable multivibrator features output pulseduration

control by three methods. In the first method,

the A input is low, and the B input goes high. In the

second method, the B input is high, and the A input

goes low. In the third method, the A input is low, the B

input is high, and the clear ( CLR) input goes high.

The output pulse duration is programmed by selecting

external resistance and capacitance values. The

external timing capacitor must be connected between

Cext and Rext/Cext (positive) and an external resistor

connected between Rext/Cext and VCC. To obtain

variable pulse durations, connect an external variable

resistance between Rext/Cext and VCC. The output

pulse duration also can be reduced by taking CLR

low.

Pulse triggering occurs at a particular voltage level

and is not directly related to the transition time of

the input pulse. The A and B inputs have Schmitt

triggers with sufficient hysteresis to handle slow input

transition rates with jitter-free triggering at the outputs.